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hcs12 microcontrollers freescale.com mc9s12dt128 device user guide covers mc9s12dt128e, mc9s12dg128e, mc9s12dj128e, mc9s12dg128, mc9s12dj128, mc9s12db128, mc9s12a128, sc515846, sc515847, sc515848, sc515849, sc101161dt, sc101161dg, sc101161dj, sc102202, sc102203, sc102204, sc102205 9s12dt128dgv2/d v02.15 05 oct 2005
device user guide ?9s12dt128dgv2/d v02.15 2 freescale semiconductor revision history version number revision date effective date author description of changes v01.00 18 jun 2001 18 june 2001 initial version (parent doc v2.03 dug for dp256). v01.01 23 july 2001 23 july 2001 updated version after review v01.02 23 sep 2001 23 sep 2001 changed partname, added pierce mode, updated electrical characteristics some minor corrections v01.03 12 oct 2001 12 oct 2001 replaced star12 by hcs12 v01.04 27 feb 2002 27 feb 2002 updated electrical spec after mc-quali?ation (iol/ioh), data for pierce, nvm reliability new document numbering. corrected typos v01.05 4 mar 2002 4 mar 2002 increased vdd to 2.35v, removed min. oscillator startup removed document order number except from cover sheet v01.06 8 july 2002 22 july 2002 added: pull-up columns to signal table, example for pll filter calculation, thermal values for junction to board and package, bgnd pin pull-up part order information global register table chip con?uration summary modi?d: reduced wait and run idd values mode of operation chapter changed leakage current for adc inputs down to +-1ua corrected: interrupt vector table enable register inconsistencies pcb layout for 80qfp vregen position v02.00 11 jan 2002 11 jan 2002 new maskset changed part number from dtb128 to dt128 functional changes: romctl changes in emulation mode 80 pin byte?ght package option available flash with 2 bit backdoor key enable additional can0 routing to pj7,6 improved bdm with sync and acknowledge capabilities new part id number improvements: signi?antly improved nvm reliability data corrections: interrupt vector table v02.01 01 feb 2002 01 feb 2002 updated block user guide versions in preface updated appendix a electrical characteristics
device user guide ?9s12dt128dgv2/d v02.15 freescale semiconductor 3 v02.02 08 mar 2002 08 mar 2002 changed xclks to pe7 in table 2-2 updated device part numbers in figure 2-1 updated bdm clock in figure 3-1 removed sim description in overview & n uposc spec in table a-15 updated electrical spec of vdd & vddpll (table a-4), iol/ioh (table a-6), c ins (table a-9), c in (table a-6 & a-15), updated interrupt pulse timing variables in table a-6 updated device part numbers in figure 2-1 added document numbers on cover page and table 0-2 v02.03 14 mar 2002 14 mar 2002 cleaned up fig. 1-1, 2-1 updated section 1.5 descriptions corrected pe assignment in table 2-2, fig. 2-5,6,7. corrected nvm sizes in sections 16, 17 added i ref spec for 1atd in table a-8 added blank check in a.3.1.5 and table a-11 updated crg spec in table a-15 v02.04 16 aug 2002 16 aug 2002 added: pull-up columns to signal table, example for pll filter calculation, thermal values for junction to board and package, bgnd pin pull-up part order information global register table chip con?uration summary device speci? info on crg modi?d: reduced wait and run idd values mode of operation chapter changed leakage current for adc inputs down to +-1ua minor modi?ation of pll frequency/ voltage gain values corrected: pin names/functions on 80 pin packages interrupt vector table enable register inconsistencies pcb layout for 80qfp vregen position v02.05 12 sep 2002 12 sep 2002 corrected: register address mismatches in 1.5.1 v02.06 06 nov 2002 06 nov 2002 removed document order no. from revision history pages renamed "preface" section to "derivative differences and document references". added details for derivatives missing can0/1/4, bdlc, iic and/or byte?ght added 2l40k mask set in section 1.6 added osc user guide in preface, ?ocument references? added oscillator clock connection to bdm in s12_core in ? 3-1 corrected several register and bit names in ?ocal enable?column of table 5.1 interrupt vector locations section hcs12 core block description: mentioned alternate clock of bdm to be equivalent to oscillator clock added new section: ?scillator (osc) block description corrected in footnote of table "pll characteristics": fosc = 4mhz version number revision date effective date author description of changes
device user guide ?9s12dt128dgv2/d v02.15 4 freescale semiconductor v02.07 29 jan 2003 29 jan 2003 added 3l40k mask set in section 1.6 corrected register entries in section 1.5.1 ?etailed memory map updated description for romctl in section 2.3.31 updated section 4.3.3 ?nsecuring the microcontroller corrected and updated device-speci? information for osc (section 8.1) & byte?ght (section 15.1) updated footnote in table a-4 ?perating conditions changed reference of vddm to vddr in section a.1.8 removed footnote on input leakage current in table a-6 ?v i/o characteristics v02.08 26 feb 2003 26 feb 2003 added part numbers mc9s12dt128e, mc9s12dg128e, and mc9s12dj128e in ?reface?and related part number references removed mask sets 0l40k and 2l40k from table 1-3 v02.09 15 oct 2003 15 oct 2003 replaced references to hcs12 core guide by the individual hcs12 block guides in table 0-2, section 1.5.1, and section 6; updated fig.3-1 ?lock connections?to show the individual hcs12 blocks corrected pim module name and document order number in table 0-2 ?ocument references corrected ect pulse accumulators description in section 1.2 ?eatures corrected kwp5 pin name in fig 2-1 112lqfp pin assignments corrected pull resistor ctrl/reset states for pe7 and pe4-pe0 in table 2.1 ?ignal properties mentioned ?12lrae?bootloader in flash section 17 corrected footnote on clamp of test pin under table a-1 ?bsolute maximum ratings corrected minimum bus frequency to 0.25mhz in table a-4 ?perating conditions replaced ?urst programming?by ?ow programming?in a.3 ?vm, flash and eeprom corrected blank check time for eeprom in table a-11 ?vm timing characteristics corrected operating frequency in table a-18 ?pi master/slave mode timing characteristics v02.10 6 feb 2004 6 feb 2004 added a128 information in ?erivative differences? 2.1 ?evice pinout? 2.2 ?ignal properties summary? fig 23-2 & fig 23-4 added lead-free package option (pve) in table 0-2 ?erivative differences for mc9s12db128?and fig 0-1 ?rder partnumber example added an ?ec quali?d?row in the ?erivative differences?tables 0-1 & 0-2. v02.11 3 may 2004 3 may 2004 added part numbers sc515846, sc515847, sc515848, and sc515849 in ?erivative differences?tables 0-1 & 0-2, section 2, and section 23. corrected and added maskset 4l40k in tables 0-1 & 0-2 and section 1.6. corrected bdlc module availability in db128 80qfp part in ?erivative differences?table 0-2. version number revision date effective date author description of changes
device user guide ?9s12dt128dgv2/d v02.15 freescale semiconductor 5 v02.12 06 dec 2004 06 dec 2004 added maskset 0l94r added items v ih,extal , v il,extal , & v hys,extal in table a-15 ?scillator characteristics removed item ?scillator?from table a-4 ?perating conditions?as it is already covered in table ?scillator characteristics? v02.13 04 mar 2005 04 mar 2005 amended feature list of a128 in table 0-1 ?erivative differences v02.14 28 apr 2005 28 apr 2005 updated cover page added part numbers sc101161dt, sc101161dg, sc101161dj, sc102202, sc102203, sc102204, & sc102205 added masksets 5l40k &1l59w changed t javg to 85 c in table a-12 ?vm reliability?& added footnote concerning data retention v02.15 05 oct 2005 05 oct 2005 updated ?vm reliability?table a-12 format with added data. added ?ure a-2 ?ypical endurance vs temperature version number revision date effective date author description of changes
device user guide ?9s12dt128dgv2/d v02.15 6 freescale semiconductor
device user guide ?9s12dt128dgv2/d v02.15 7 freescale semiconductor table of contents section 1 introduction 1.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5 device memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.1 detailed register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.6 part id assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 section 2 signal description 2.1 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.2 signal properties summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.1 extal, xtal ?oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.2 reset ?external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.3 test ?test pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.4 xfc ?pll loop filter pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.5 bkgd / taghi / modc ?background debug, tag high, and mode pin . . . . . 64 2.3.6 pad[15] / an1[7] / etrig1 ?port ad input pin [15] . . . . . . . . . . . . . . . . . . . . . 65 2.3.7 pad[14:8] / an1[6:0] ?port ad input pins [14:8]. . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.8 pad[7] / an0[7] / etrig0 ?port ad input pin [7] . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.9 pad[6:0] / an0[6:0] ?port ad input pins [6:0]. . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.10 pa[7:0] / addr[15:8] / data[15:8] ?port a i/o pins . . . . . . . . . . . . . . . . . . . . 65 2.3.11 pb[7:0] / addr[7:0] / data[7:0] ?port b i/o pins . . . . . . . . . . . . . . . . . . . . . . 65 2.3.12 pe7 / noacc / xclks ?port e i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.13 pe6 / modb / ipipe1 ?port e i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.14 pe5 / moda / ipipe0 ?port e i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.15 pe4 / eclk ?port e i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.16 pe3 / lstrb / taglo ?port e i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.17 pe2 / r/w ?port e i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.18 pe1 / irq ?port e input pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.19 pe0 / xirq ?port e input pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.20 ph7 / kwh7 ?port h i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
device user guide ?9s12dt128dgv2/d v02.15 8 freescale semiconductor 2.3.21 ph6 / kwh6 ?port h i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.22 ph5 / kwh5 ?port h i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.23 ph4 / kwh4 ?port h i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.24 ph3 / kwh3 / ss1 ?port h i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.25 ph2 / kwh2 / sck1 ?port h i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.26 ph1 / kwh1 / mosi1 ?port h i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.27 ph0 / kwh0 / miso1 ?port h i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.28 pj7 / kwj7 / txcan4 / scl / txcan0 ?port j i/o pin 7. . . . . . . . . . . . . . . 68 2.3.29 pj6 / kwj6 / rxcan4 / sda / rxcan0 ?port j i/o pin 6 . . . . . . . . . . . . . . 69 2.3.30 pj[1:0] / kwj[1:0] ?port j i/o pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.31 pk7 / ecs / romctl ?port k i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.32 pk[5:0] / xaddr[19:14] ?port k i/o pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.33 pm7 / bf_pslm / txcan4 ?port m i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.34 pm6 / bf_perr / rxcan4 ?port m i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.35 pm5 / bf_prok / txcan0 / txcan4 / sck0 ?port m i/o pin 5 . . . . . . . . . . 69 2.3.36 pm4 / bf_psyn / rxcan0 / rxcan4/ mosi0 ?port m i/o pin 4. . . . . . . . . . 70 2.3.37 pm3 / tx_bf / txcan1 / txcan0 / ss0 ?port m i/o pin 3 . . . . . . . . . . . . . . 70 2.3.38 pm2 / rx_bf / rxcan1 / rxcan0 / miso0 ?port m i/o pin 2. . . . . . . . . . . . 70 2.3.39 pm1 / txcan0 / txb ?port m i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.3.40 pm0 / rxcan0 / rxb ?port m i/o pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.3.41 pp7 / kwp7 / pwm7 ?port p i/o pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.3.42 pp6 / kwp6 / pwm6 ?port p i/o pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.3.43 pp5 / kwp5 / pwm5 ?port p i/o pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.3.44 pp4 / kwp4 / pwm4 ?port p i/o pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.3.45 pp3 / kwp3 / pwm3 / ss1 ?port p i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.3.46 pp2 / kwp2 / pwm2 / sck1 ?port p i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . 71 2.3.47 pp1 / kwp1 / pwm1 / mosi1 ?port p i/o pin 1. . . . . . . . . . . . . . . . . . . . . . . . 71 2.3.48 pp0 / kwp0 / pwm0 / miso1 ?port p i/o pin 0. . . . . . . . . . . . . . . . . . . . . . . . 71 2.3.49 ps7 / ss0 ?port s i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.3.50 ps6 / sck0 ?port s i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.3.51 ps5 / mosi0 ?port s i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.3.52 ps4 / miso0 ?port s i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.3.53 ps3 / txd1 ?port s i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.3.54 ps2 / rxd1 ?port s i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.3.55 ps1 / txd0 ?port s i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.3.56 ps0 / rxd0 ?port s i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
device user guide ?9s12dt128dgv2/d v02.15 9 freescale semiconductor 2.3.57 pt[7:0] / ioc[7:0] ?port t i/o pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.4 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.4.1 vddx,vssx ?power & ground pins for i/o drivers . . . . . . . . . . . . . . . . . . . . . 73 2.4.2 vddr, vssr ?power & ground pins for i/o drivers & for internal voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.4.3 vdd1, vdd2, vss1, vss2 ?internal logic power supply pins . . . . . . . . . . . . 73 2.4.4 vdda, vssa ?power supply pins for atd and vreg . . . . . . . . . . . . . . . . . . 74 2.4.5 vrh, vrl ?atd reference voltage input pins . . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.6 vddpll, vsspll ?power supply pins for pll . . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.7 vregen ?on chip voltage regulator enable . . . . . . . . . . . . . . . . . . . . . . . . . 74 section 3 system clock description 3.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 section 4 modes of operation 4.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 4.2 chip configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.3 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 4.3.1 securing the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.3.2 operation of the secured microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.3.3 unsecuring the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.4.1 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.4.2 pseudo stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.4.3 wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.4.4 run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 section 5 resets and interrupts 5.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 5.2 vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.2.1 vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.3 effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.1 i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 5.3.2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 section 6 hcs12 core block description 6.1 cpu block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
device user guide ?9s12dt128dgv2/d v02.15 10 freescale semiconductor 6.1.1 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.2 hcs12 module mapping control (mmc) block description . . . . . . . . . . . . . . . . . . . 85 6.2.1 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3 hcs12 multiplexed external bus interface (mebi) block description . . . . . . . . . . . 85 6.3.1 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.4 hcs12 interrupt (int) block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.5 hcs12 background debug module (bdm) block description . . . . . . . . . . . . . . . . . 86 6.5.1 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.6 hcs12 breakpoint (bkp) block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 section 7 clock and reset generator (crg) block description 7.1 device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 section 8 oscillator (osc) block description 8.1 device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 section 9 enhanced capture timer (ect) block description section 10 analog to digital converter (atd) block description section 11 inter-ic bus (iic) block description section 12 serial communications interface (sci) block description section 13 serial peripheral interface (spi) block description section 14 j1850 (bdlc) block description section 15 byteflight (bf) block description 15.1 device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 section 16 pulse width modulator (pwm) block description section 17 flash eeprom 128k block description section 18 eeprom 2k block description section 19 ram block description
device user guide ?9s12dt128dgv2/d v02.15 11 freescale semiconductor section 20 mscan block description section 21 port integration module (pim) block description section 22 voltage regulator (vreg) block description section 23 printed circuit board layout proposal appendix a electrical characteristics a.1 general. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 a.1.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 a.1.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 a.1.3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 a.1.4 current injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 a.1.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 a.1.6 esd protection and latch-up immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 a.1.7 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 a.1.8 power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 101 a.1.9 i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 a.1.10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 a.2 atd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 a.2.1 atd operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 a.2.2 factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 a.2.3 atd accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 a.3 nvm, flash and eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 a.3.1 nvm timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 a.3.2 nvm reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 a.4 voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 a.5 reset, oscillator and pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 a.5.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 a.5.2 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 a.5.3 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 a.6 mscan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 a.7 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 a.7.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 a.7.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
device user guide ?9s12dt128dgv2/d v02.15 12 freescale semiconductor a.8 external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 a.8.1 general multiplexed bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 appendix b package information b.1 general. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 b.2 112-pin lqfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 b.3 80-pin qfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
device user guide ?9s12dt128dgv2/d v02.15 13 freescale semiconductor list of figures figure 0-1 order partnumber example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 1-1 mc9s12dt128 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 1-2 mc9s12dt128 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 2-1 pin assignments 112 lqfp for mc9s12dt128e, mc9s12dt128, mc9s12dg128e, mc9s12dg128, mc9s12dj128e, mc9s12dj128, mc9s12db128 mc9s12a128, sc515846, sc515847, sc515848, sc515849, sc101161dt, sc101161dg, sc101161dj, sc102202, sc102203, sc102204, and sc102205 . . . . . . . . . . . . . . . . . . 58 figure 2-2 pin assignments in 80 qfp for mc9s12dg128e, mc9s12dg128, mc9s12dj128e, mc9s12dj128, mc9s12a128, sc515847, sc515848, sc101161dg, sc101161dj, sc102203, and sc102204 bondout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 2-3 pin assignments in 80 qfp for mc9s12db128, sc515846, and sc102202 bond - out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 2-4 pll loop filter connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 2-5 colpitts oscillator connections (pe7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 2-6 pierce oscillator connections (pe7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 2-7 external clock connections (pe7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 3-1 clock connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 23-1 recommended pcb layout for 112lqfp colpitts oscillator . . . . . . . . . . . . 91 figure 23-2 recommended pcb layout for 80qfp (mc9s12dg128e, mc9s12dg128, mc9s12dj128e, mc9s12dj128, mc9s12a128, sc515847, sc515848, sc101161dg, sc101161dj, sc102203, and sc102204) colpitts oscillator . . . . . . . . . . . . . . . . . . . . . . 92 figure 23-3 recommended pcb layout for 112lqfp pierce oscillator . . . . . . . . . . . . . 93 figure 23-4 recommended pcb layout for 80qfp (mc9s12dg128e, mc9s12dg128, mc9s12dj128e, mc9s12dj128, mc9s12a128, sc515847, sc515848, sc101161dg, sc101161dj, sc102203, and sc102204) pierce oscillator . . . . . . . . . . . . . . . . . . . . . . . 94 figure 23-5 recommended pcb layout for 80qfp (mc9s12db128, sc515846, and sc102202) pierce oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure a-1 atd accuracy definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure a-2 typical endurance vs temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure a-3 basic pll functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure a-4 jitter definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure a-5 maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure a-6 spi master timing (cpha = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure a-7 spi master timing (cpha =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure a-8 spi slave timing (cpha = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure a-9 spi slave timing (cpha =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
device user guide ?9s12dt128dgv2/d v02.15 14 freescale semiconductor figure a-10 general external bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 23-6 112-pin lqfp mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . 138
device user guide ?9s12dt128dgv2/d v02.15 15 freescale semiconductor list of tables table 0-1 derivative differences1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 0-2 derivative differences for mc9s12db1281. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 0-3 document references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 1-1 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 $0000 - $000fmebi map 1 of 3 (hcs12 multiplexed external bus interface) ................... 32 $0010 - $0014 mmc map 1 of 4 (hcs12 module mapping control) ................................. 32 $0015 - $0016 int map 1 of 2 (hcs12 interrupt) .............................................................. 33 $0017 - $0017mmc map 2 of 4 (hcs12 module mapping control) .................................. 33 $0018 - $0019reserved ..................................................................................................... 33 $001a - $001b device id register ( (table 1-3) ) ............................................................... 33 $001c - $001d mmc map 3 of 4 (hcs12 module mapping control, (table 1-4) ) ............ 33 $001e - $001emebi map 2 of 3 (hcs12 multiplexed external bus interface) .................. 33 $001f - $001fint map 2 of 2 (hcs12 interrupt) ............................................................... 34 $0020 - $0027 reserved .................................................................................................... 34 $0028 - $002f bkp (hcs12 breakpoint) ........................................................................... 34 $0030 - $0031 mmc map 4 of 4 (hcs12 module mapping control) ................................. 34 $0032 - $0033 mebi map 3 of 3 (hcs12 multiplexed external bus interface) .................. 34 $0034 - $003f crg (clock and reset generator) ............................................................ 35 $0040 - $007f ect (enhanced capture timer 16 bit 8 channels) ................................... 35 $0080 - $009f atd0 (analog to digital converter 10 bit 8 channel) ................................ 38 $00a0 - $00c7 pwm (pulse width modulator 8 bit 8 channel) ........................................ 39 $00c8 - $00cf sci0 (asynchronous serial interface) ...................................................... 41 $00d0 - $00d7 sci1 (asynchronous serial interface) ....................................................... 41 $00d8 - $00df spi0 (serial peripheral interface) ............................................................. 42 $00e0 - $00e7 iic (inter ic bus) ....................................................................................... 42 $00e8 - $00ef bdlc (byte level data link controller j1850) ......................................... 43 $00f0 - $00f7 spi1 (serial peripheral interface) .............................................................. 43 $00f8 - $00ff reserved ................................................................................................... 43 $0100 - $010f flash control register (fts128k2) .............................................................. 44 $0110 - $011b eeprom control register (eets2k) .......................................................... 44 $011c - $011f reserved for ram control register .......................................................... 45 $0120 - $013f atd1 (analog to digital converter 10 bit 8 channel) ................................ 45 $0140 - $017f can0 (motorola scalable can - mscan) ................................................ 46
device user guide ?9s12dt128dgv2/d v02.15 16 freescale semiconductor table 1-2 detailed mscan foreground receive and transmit buffer layout. . . . . . . . 47 $0180 - $01bf can1 (motorola scalable can - mscan) ................................................ 48 $01c0 - $01ff reserved ................................................................................................... 49 $0200 - $023f reserved .................................................................................................... 49 $0240 - $027f pim (port integration module) .................................................................... 50 $0280 - $02bf can4 (motorola scalable can - mscan) ................................................ 52 $02c0 - $02ff reserved ................................................................................................... 53 $0300 - $035f byteflight .................................................................................................... 53 $0360 - $03ff reserved ................................................................................................... 55 table 1-3 assigned part id numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 1-4 memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 2-1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 2-2 mc9s12dt128 power and ground connection summary . . . . . . . . . . . . . . . 72 table 4-1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 4-2 clock selection based on pe7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 4-3 voltage regulator vregen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 5-1 interrupt vector locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 23-1 suggested external component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table a-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table a-2 esd and latch-up test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table a-3 esd and latch-up protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . 100 table a-4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table a-5 thermal package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table a-6 5v i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table a-7 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table a-8 atd operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table a-9 atd electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table a-10 atd conversion performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table a-11 nvm timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table a-12 nvm reliability characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table a-13 voltage regulator recommended load capacitances . . . . . . . . . . . . . . . . . 117 table a-14 startup characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table a-15 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table a-16 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table a-17 mscan wake-up pulse characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table a-18 spi master mode timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
device user guide ?9s12dt128dgv2/d v02.15 17 freescale semiconductor table a-19 spi slave mode timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table a-20 expanded bus timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
device user guide ?9s12dt128dgv2/d v02.15 18 freescale semiconductor
device user guide ?9s12dt128dgv2/d v02.15 19 freescale semiconductor derivative differences and document references derivative differences (table 0-1) and (table 0-2) show the availability of peripheral modules on the various derivatives. for details about the compatibility within the mc9s12d-family refer also to engineering bulletin eb386. table 0-2 derivative differences for mc9s12db128 1 table 0-1 derivative differences 1 modules mc9s12dt128e 3 mc9s12dt128 sc515849 4 sc101161dt 5 sc102205 6 mc9s12dg128e 3 mc9s12dg128 sc515847 4 sc101161dg 5 sc102203 6 mc9s12dj128e 3 mc9s12dj128 sc515848 4 sc101161dj 5 sc102204 6 mc9s12a128 # of cans 3 2 2 0 can4 ? ? ? ? can1 ? ? ? ? can0 ? ? ? ? j1850/bdlc ? ? ? ? iic ? ? ? ? byte?ght ? ? ? ? package 112 lqfp 112 lqfp/80 qfp 2 112 lqfp/80 qfp 2 112 lqfp/80 qfp 2 package code pv pv/fu pv/fu pv/fu mask set 1l40k 3 , 3l40k, 0l94r, 4l40k 4 , 1l59w 5 , 5l40k 6 1l40k 3 , 3l40k, 0l94r, 4l40k 4 , 1l59w 5 , 5l40k 6 1l40k 3 , 3l40k, 0l94r, 4l40k 4 , 1l59w 5 , 5l40k 6 3l40k, 0l94r temp options m, v, c m, v, c m, v, c c aec quali?d ye s ye s ye s no notes an errata exists contact sales of?e an errata exists contact sales of?e an errata exists contact sales of?e an errata exists contact sales of?e modules mc9s12db128 sc515846 4 sc102202 6 mc9s12db128 sc515846 4 sc102202 6 # of cans 2 0 can4 ? ? can1 ? ? can0 ? ? j1850/bdlc ? ? iic ? ? byte?ght ? ? package 112 lqfp 80 qfp 2 package code pv/pve fu
device user guide ?9s12dt128dgv2/d v02.15 20 freescale semiconductor note: 1. ? : available for this device, ? : not available for this device. 2. 80 pin bond-out for mc9s12dg128e, mc9s12dg128, mc9s12dj128e, mc9s12dj128, mc9s12a128, sc515847, sc515848, sc101161dg, sc101161dj, sc102203, and sc102204 is the same; mc9s12db128, sc515846, and sc102202 have a different bond-out. 3. part numbers mc9s12dt128e, mc9s12dg128e, and mc9s12dj128e are associated with the mask set 1l40k. 4. part numbers sc515846, sc515847, sc515848, and sc515849 are associated with the mask set 4l40k. 5. part numbers sc101161dt, sc101161dg, sc101161dj are associated with the mask set 1l59w. 6. part numbers sc102202, sc102203, sc102204, and sc102205 are associated with the mask set 5l40k which is not for volume production. the following figure provides an ordering number example for the mc9s12d128 devices. figure 0-1 order partnumber example the following items should be considered when using a derivative. registers do not write or read can0 registers (after reset: address range $0140 - $017f), if using a derivative without can0 (see (table 0-1) and (table 0-2) ). do not write or read can1 registers (after reset: address range $0180 - $01bf), if using a derivative without can1 (see (table 0-1) and (table 0-2) ). do not write or read can4 registers (after reset: address range $0280 - $02bf), if using a derivative without can4 (see (table 0-1) and (table 0-2) ). do not write or read bdlc registers (after reset: address range $00e8 - $00ef), if using a derivative without bdlc (see (table 0-1) and (table 0-2) ). do not write or read iic registers (after reset: address range $00e0 - $00e7), if using a derivative without iic (see (table 0-1) and (table 0-2) ). mask set 3l40k, 0l94r, 4l40k 4 , 5l40k 6 3l40k, 0l94r, 4l40k 4 , 5l40k 6 temp options m, v, c/m, v m, v, c aec quali?d ye s ye s notes an errata exists contact sales of?e an errata exists contact sales of?e modules mc9s12db128 sc515846 4 sc102202 6 mc9s12db128 sc515846 4 sc102202 6 mc9s12 dj128 c fu package option temperature option device title controller family temperature options c = -40?c to 85?c v = -40?c to 105?c m = -40?c to 125?c package options fu = 80qfp pv = 112lqfp pve = lead-free 112lqfp
device user guide ?9s12dt128dgv2/d v02.15 21 freescale semiconductor do not write or read byteflight registers (after reset: address range $0300 - $035f), if using a derivative without byteflight registers (see (table 0-1) and (table 0-2) ). interrupts fill the four can0 interrupt vectors ($ffb0 - $ffb7) according to your coding policies for unused interrupts, if using a derivative without can0 (see (table 0-1) and (table 0-2) ). fill the four can1 interrupt vectors ($ffa8 - $ffaf) according to your coding policies for unused interrupts, if using a derivative without can1 (see (table 0-1) and (table 0-2) ). fill the four can4 interrupt vectors ($ff90 - $ff97) according to your coding policies for unused interrupts, if using a derivative without can4 (see (table 0-1) and (table 0-2) ). fill the bdlc interrupt vector ($ffc2, $ffc3) according to your coding policies for unused interrupts, if using a derivative without bdlc (see (table 0-1) and (table 0-2) ). fill the iic interrupt vector ($ffc0, $ffc1) according to your coding policies for unused interrupts, if using a derivative without iic (see (table 0-1) and (table 0-2) ). fill the four byteflight interrupt vectors ($ffa0 - $ffa7) according to your coding policies for unused interrupts, if using a derivative without byteflight (see (table 0-1) and (table 0-2) ). ports the can0 pin functionality (txcan0, rxcan0) is not available on port pj7, pj6, pm5, pm4, pm3, pm2, pm1 and pm0, if using a derivative without can0 (see (table 0-1) and (table 0-2) ). the can1 pin functionality (txcan1, rxcan1) is not available on port pm3 and pm2, if using a derivative without can1 (see (table 0-1) and (table 0-2) ). the can4 pin functionality (txcan4, rxcan4) is not available on port pj7, pj6, pm7, pm6, pm5 and pm4, if using a derivative without can4 (see (table 0-1) and (table 0-2) ). the bdlc pin functionality (txb, rxb) is not available on port pm1 and pm0, if using a derivative without bdlc (see (table 0-1) and (table 0-2) ). the iic pin functionality (scl, sca) is not available on port pj7 and pj6, if using a derivative without iic (see (table 0-1) and (table 0-2) ). the byteflight pin functionality (bf_pslm, bf_perr, bf_prok, bf_psyn, tx_bf, rx_bf) is not available on port pm7, pm6, pm5, pm4, pm3 and pm2, if using a derivative without byteflight (see (table 0-1) and (table 0-2) ). do not write modrr1 and modrr0 bit of module routing register (pim_9dtb128 block user guide), if using a derivative without can0 (see (table 0-1) and (table 0-2) ). do not write modrr3 and modrr2 bit of module routing register (pim_9dtb128 block user guide), if using a derivative without can4 (see (table 0-1) and (table 0-2) ). pins not available in 80 pin qfp package for mc9s12dg128e, mc9s12dg128, mc9s12dj128e, mc9s12dj128, mc9s12a128, sc515847, sc515848, sc101161dg, sc101161dj, sc102203, and sc102204
device user guide ?9s12dt128dgv2/d v02.15 22 freescale semiconductor port h in order to avoid floating nodes the ports should be either configured as outputs by setting the data direction register (ddrh at base+$0262) to $ff, or enabling the pull resistors by writing a $ff to the pull enable register (perh at base+$0264). port j[1:0] port j pull-up resistors are enabled out of reset on all four pins (7:6 and 1:0). therefore care must be taken not to disable the pull enables on pj[1:0] by clearing the bits perj1 and perj0 at base+$026c. port k port k pull-up resistors are enabled out of reset, i.e. bit 7 = puke = 1 in the register pucr at base+$000c. therefore care must be taken not to clear this bit. port m[7:6] pm7:6 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. port p6 pp6 must be configured as output or its pull resistor must be enabled to avoid a floating input. port s[7:4] ps7:4 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. pad[15:8] (atd1 channels) out of reset the atd1 is disabled preventing current flows in the pins. do not modify the atd1 registers! pins not available in 80 pin qfp package for mc9s12db128, sc515846, and sc102202 port h in order to avoid floating nodes the ports should be either configured as outputs by setting the data direction register (ddrh at base+$0262) to $ff, or enabling the pull resistors by writing a $ff to the pull enable register (perh at base+$0264). port j[7:6, 1:0] port j pull-up resistors are enabled out of reset on all four pins (7:6 and 1:0). therefore care must be taken not to disable the pull enables on pj[7:6, 1:0] by clearing the bits perj7, perj6, perj1 and perj0 at base+$026c. port k port k pull-up resistors are enabled out of reset, i.e. bit 7 = puke = 1 in the register pucr at base+$000c. therefore care must be taken not to clear this bit. port m[1:0] pm1:0 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. port p6 pp6 must be configured as output or its pull resistor must be enabled to avoid a floating input.
device user guide ?9s12dt128dgv2/d v02.15 23 freescale semiconductor port s[3:2] ps3:2 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. pad[15:8] (atd1 channels) out of reset the atd1 is disabled preventing current flows in the pins. do not modify the atd1 registers! document references the device user guide provides information about the mc9s12dt128 device made up of standard hcs12 blocks and the hcs12 processor core. this document is part of the customer documentation. a complete set of device manuals also includes all the individual block user guides of the implemented modules. in a effort to reduce redundancy all module specific information is located only in the respective block user guide. if applicable, special implementation details of the module are given in the block description sections of this document. see table 0-3 for names and versions of the referenced documents throughout the device user guide. table 0-3 document references user guide version document order number hcs12 cpu reference manual v02 s12cpuv2/d hcs12 module mapping control (mmc) block guide v04 s12mmcv4/d hcs12 multiplexed external bus interface (mebi) block guide v03 s12mebiv3/d hcs12 interrupt (int) block guide v01 s12intv1/d hcs12 background debug module (bdm) block guide v04 s12bdmv4/d hcs12 breakpoint (bkp) block guide v01 s12bkpv1/d clock and reset generator (crg) block user guide v04 s12crgv4/d oscillator (osc) block user guide v02 s12oscv2/d enhanced capture timer 16 bit 8 channel (ect_16b8c) block user guide v01 s12ect16b8cv1/d analog to digital converter 10 bit 8 channel (atd_10b8c) block user guide v02 s12atd10b8cv2/d inter ic bus (iic) block user guide v02 s12iicv2/d asynchronous serial interface (sci) block user guide v02 s12sciv2/d serial peripheral interface (spi) block user guide v02 s12spiv2/d pulse width modulator 8 bit 8 channel (pwm_8b8c) block user guide v01 s12pwm8b8cv1/d 128k byte flash (fts128k) block user guide v02 s12fts128kv2/d 2k byte eeprom (eets2k) block user guide v01 s12eets2kv1/d byte level data link controller -j1850 (bdlc) block user guide v01 s12bdlcv1/d motorola scalable can (mscan) block user guide v02 s12mscanv2/d voltage regulator (vreg) block user guide v01 s12vregv1/d port integration module (pim_9dtb128) block user guide v02 s12dtb128pimv2/d byteflight (bf) block user guide v01 s12bfv1/d
device user guide ?9s12dt128dgv2/d v02.15 24 freescale semiconductor
device user guide ?9s12dt128dgv2/d v02.15 25 freescale semiconductor section 1 introduction 1.1 overview the mc9s12dt128 microcontroller unit (mcu) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (hcs12 cpu), 128k bytes of flash eeprom, 8k bytes of ram, 2k bytes of eeprom, two asynchronous serial communications interfaces (sci), two serial peripheral interfaces (spi), an 8-channel ic/oc enhanced capture timer, two 8-channel, 10-bit analog-to-digital converters (adc), an 8-channel pulse-width modulator (pwm), a digital byte data link controller (bdlc), 29 discrete digital i/o channels (port a, port b, port k and port e), 20 discrete digital i/o lines with interrupt and wakeup capability, three can 2.0 a, b software compatible modules (mscan12), a byteflight module and an inter-ic bus. the mc9s12dt128 has full 16-bit data paths throughout. however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. the inclusion of a pll circuit allows power consumption and performance to be adjusted to suit operational requirements. 1.2 features hcs12 core 16-bit hcs12 cpu i. upward compatible with m68hc11 instruction set ii. interrupt stacking and programmer? model identical to m68hc11 iii. 20-bit alu iv. instruction queue v. enhanced indexed addressing mebi (multiplexed external bus interface) mmc (module mapping control) int (interrupt control) bkp (breakpoints) bdm (background debug module) crg (clock and reset generator) choice of low current colpitts oscillator or standard pierce oscillator pll cop watchdog real time interrupt clock monitor 8-bit and 4-bit ports with interrupt functionality
device user guide ?9s12dt128dgv2/d v02.15 26 freescale semiconductor digital filtering programmable rising or falling edge trigger memory 128k flash eeprom 2k byte eeprom 8k byte ram two 8-channel analog-to-digital converters 10-bit resolution external conversion trigger capability three 1m bit per second, can 2.0 a, b software compatible modules five receive and three transmit buffers flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit four separate interrupt channels for rx, tx, error and wake-up low-pass filter wake-up function loop-back for self test operation enhanced capture timer 16-bit main counter with 7-bit prescaler 8 programmable input capture or output compare channels four 8-bit or two 16-bit pulse accumulators 8 pwm channels programmable period and duty cycle 8-bit 8-channel or 16-bit 4-channel separate control for each pulse width and duty cycle center-aligned or left-aligned outputs programmable clock select logic with a wide range of frequencies fast emergency shutdown input usable as interrupt inputs serial interfaces two asynchronous serial communications interfaces (sci) two synchronous serial peripheral interface (spi) byteflight byte data link controller (bdlc)
device user guide ?9s12dt128dgv2/d v02.15 27 freescale semiconductor sae j1850 class b data communications network interface compatible and iso compatible for low-speed (<125 kbps) serial data communications in automotive applications inter-ic bus (iic) compatible with i2c bus standard multi-master operation software programmable for one of 256 different serial clock frequencies 112-pin lqfp and 80-pin qfp package options i/o lines with 5v input and drive capability 5v a/d converter inputs operation at 50mhz equivalent to 25mhz bus speed development support single-wire background debug mode on-chip hardware breakpoints 1.3 modes of operation user modes normal and emulation operating modes normal single-chip mode normal expanded wide mode normal expanded narrow mode emulation expanded wide mode emulation expanded narrow mode special operating modes special single-chip mode with active background debug mode special test mode ( freescale use only ) special peripheral mode ( freescale use only ) low power modes stop mode pseudo stop mode wait mode
device user guide ?9s12dt128dgv2/d v02.15 28 freescale semiconductor 1.4 block diagram figure 1-1 shows a block diagram of the mc9s12dt128 device.
device user guide ?9s12dt128dgv2/d v02.15 29 freescale semiconductor figure 1-1 mc9s12dt128 block diagram 128k byte flash eeprom 8k byte ram enhanced capture reset extal xtal v dd1,2 v ss1,2 sci0 2k byte eeprom bkgd r/ w modb xirq noacc/ xclks system integration module (sim) vddr cpu periodic interrupt cop watchdog clock monitor single-wire background breakpoints pll vsspll xfc vddpll multiplexed address/data bus vdda vssa vrh vrl atd0 multiplexed wide bus multiplexed v ddx v ssx internal logic 2.5v narrow bus ppage v ddpll v sspll pll 2.5v irq lstrb eclk moda pa 4 pa 3 pa 2 pa 1 pa 0 pa 7 pa 6 pa 5 test addr12 addr11 addr10 addr9 addr8 addr15 addr14 addr13 data12 data11 data10 data9 data8 data15 data14 data13 pb4 pb3 pb2 pb1 pb0 pb7 pb6 pb5 addr4 addr3 addr2 addr1 addr0 addr7 addr6 addr5 data4 data3 data2 data1 data0 data7 data6 data5 data4 data3 data2 data1 data0 data7 data6 data5 pe3 pe4 pe5 pe6 pe7 pe0 pe1 pe2 an2 an6 an0 an7 an1 an3 an4 an5 pad03 pad04 pad05 pad06 pad07 pad00 pad01 pad02 ioc2 ioc6 ioc0 ioc7 ioc1 ioc3 ioc4 ioc5 pt3 pt4 pt5 pt6 pt7 pt0 pt1 pt2 vrh vrl vdda vssa vrh vrl atd1 an2 an6 an0 an7 an1 an3 an4 an5 pad11 pad12 pad13 pad14 pad15 pad08 pad09 pad10 vdda vssa rxd txd miso mosi ps3 ps4 ps5 ps0 ps1 ps2 sci1 rxd txd pwm2 pwm6 pwm0 pwm7 pwm1 pwm3 pwm4 pwm5 pp3 pp4 pp5 pp6 pp7 pp0 pp1 pp2 pix2 pix0 pix1 pix3 romctl ecs pk3 pk7 pk0 pk1 xaddr17 ecs romctl xaddr14 xaddr15 xaddr16 sck ss ps6 ps7 spi0 iic sda scl pj6 pj7 can0 rxcan txcan pm1 pm0 can1 rxcan txcan pm2 pm3 pm4 pm5 pm6 pm7 kwh2 kwh6 kwh0 kwh7 kwh1 kwh3 kwh4 kwh5 ph3 ph4 ph5 ph6 ph7 ph0 ph1 ph2 kwj0 kwj1 pj0 pj1 i/o driver 5v v dda v ssa a/d converter 5v & ddra ddrb pta ptb ddre pte ad1 ad0 ptk ddrk ptt ddrt ptp ddrp pts ddrs ptm ddrm pth ddrh ptj ddrj pk2 bdlc rxb txb clock and reset generation module voltage regulator vssr debug module vdd1,2 vss1,2 vregen v ddr v ssr voltage regulator 5v & i/o can0,4 rxcan txcan miso mosi sck ss spi1 pix4 pix5 pk4 pk5 xaddr18 xaddr19 voltage regulator reference kwp2 kwp6 kwp0 kwp7 kwp1 kwp3 kwp4 kwp5 kwj6 kwj7 timer (j1850) signals shown in bold are not available in any of the two the 80 pin package options module to port routing rx_bf tx_bf byte- bf_psyn bf_prok bf_perr bf_pslm flight signals shown in bold-italics are not available in the 80 pin package option for dg and dj128 signals shown in italics are not available in the 80 pin package option for b128
device user guide ?9s12dt128dgv2/d v02.15 30 freescale semiconductor 1.5 device memory map (table 1-1) and (figure 1-2) show the device memory map of the mc9s12dt128 after reset. note that after reset the eeprom ($0000 ? $07ff) is hidden by the register space ($0000 - $03ff) and the ram ($0000 - $1fff). the bottom 1k bytes of ram ($0000 - $03ff) are hidden by the register space . table 1-1 device memory map address module size (bytes) $0000 ?$0017 core (ports a, b, e, modes, inits, test) 24 $0018 ?$0019 reserved 2 $001a ?$001b device id register (partid) 2 $001c ?$001f core (memsiz, irq, hprio) 4 $0020 ?$0027 reserved 8 $0028 ?$002f core (background debug module) 8 $0030 ?$0033 core (ppage, port k) 4 $0034 ?$003f clock and reset generator (pll, rti, cop) 12 $0040 ?$007f enhanced capture timer 16-bit 8 channels 64 $0080 ?$009f analog to digital converter 10-bit 8 channels (atd0) 32 $00a0 ?$00c7 pulse width modulator 8-bit 8 channels (pwm) 40 $00c8 ?$00cf serial communications interface (sci0) 8 $00d0 ?$00d7 serial communications interface (sci1) 8 $00d8 ?$00df serial peripheral interface (spi0) 8 $00e0 ?$00e7 inter ic bus 8 $00e8 ?$00ef byte level data link controller (bdlc) 8 $00f0 ?$00f7 serial peripheral interface (spi1) 8 $00f8 ?$00ff reserved 8 $0100 ?$010f flash control register 16 $0110 ?$011b eeprom control register 12 $011c ?$011f reserved 4 $0120 ?$013f analog to digital converter 10-bit 8 channels (atd1) 32 $0140 ?$017f motorola scalable can (can0) 64 $0180 ?$01bf motorola scalable can (can1) 64 $01c0 ?$01ff reserved 64 $0200 ?$023f reserved 64 $0240 ?$027f port integration module (pim) 64 $0280 ?$02bf motorola scalable can (can4) 64 $02c0 ?$02ff reserved 64 $0300 ?$035f byte?ght (bf) 96 $0360 ?$03ff reserved 160 $0000 ?$07ff eeprom array 2048 $0000 ?$1fff ram array 8192 $4000 ?$7fff fixed flash eeprom array incl. 0.5k, 1k, 2k or 4k protected sector at start 16384 $8000 ?$bfff flash eeprom page window 16384
device user guide ?9s12dt128dgv2/d v02.15 31 freescale semiconductor figure 1-2 mc9s12dt128 memory map $c000 ?$ffff fixed flash eeprom array incl. 0.5k, 1k, 2k or 4k protected sector at end and 256 bytes of vector space at $ff80 ? $ffff 16384 table 1-1 device memory map address module size (bytes) $0000 $ffff $c000 $8000 $4000 $0400 $0800 $1000 $2000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window eight * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $2000 $3fff 8k bytes ram mappable to any 8k boundary $0800 $0fff 2k bytes eeprom mappable to any 2k boundary $0000 $03ff 1k register space mappable to any 2k boundary the address does not show the map after reset, but a useful map. after reset the map is: $0000 ?$03ff: register space $0000 ?$1fff: 8k ram $0000 ?$07ff: 2k eeprom (not visible)
device user guide ?9s12dt128dgv2/d v02.15 32 freescale semiconductor 1.5.1 detailed register map $0000 - $000f mebi map 1 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0000 porta read: bit 7 6 5 4 3 2 1 bit 0 write: $0001 portb read: bit 7 6 5 4 3 2 1 bit 0 write: $0002 ddra read: bit 7 6 5 4 3 2 1 bit 0 write: $0003 ddrb read: bit 7 6 5 4 3 2 1 bit 0 write: $0004 reserved read: 0 0 0 0 0 0 0 0 write: $0005 reserved read: 0 0 0 0 0 0 0 0 write: $0006 reserved read: 0 0 0 0 0 0 0 0 write: $0007 reserved read: 0 0 0 0 0 0 0 0 write: $0008 porte read: bit 7 6 5 4 3 2 bit 1 bit 0 write: $0009 ddre read: bit 7 6 5 4 3 bit 2 0 0 write: $000a pear read: noacce 0 pipoe neclk lstre rdwe 0 0 write: $000b mode read: modc modb moda 0 ivis 0 emk eme write: $000c pucr read: pupke 0 0 pupee 0 0 pupbe pupae write: $000d rdriv read: rdpk 0 0 rdpe 0 0 rdpb rdpa write: $000e ebictl read: 0 0 0 0 0 0 0 estr write: $000f reserved read: 0 0 0 0 0 0 0 0 write: $0010 - $0014 mmc map 1 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0010 initrm read: ram15 ram14 ram13 ram12 ram11 0 0 ramhal write: $0011 initrg read: 0 reg14 reg13 reg12 reg11 0 0 0 write: $0012 initee read: ee15 ee14 ee13 ee12 ee11 0 0 eeon write: $0013 misc read: 0 0 0 0 exstr1 exstr0 romhm romon write: $0014 reserved read: 0 0 0 0 0 0 0 0 write:
device user guide ?9s12dt128dgv2/d v02.15 33 freescale semiconductor $0015 - $0016 int map 1 of 2 (hcs12 interrupt) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0015 itcr read: 0 0 0 wrint adr3 adr2 adr1 adr0 write: $0016 itest read: inte intc inta int8 int6 int4 int2 int0 write: $0017 - $0017 mmc map 2 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0017 mtst1 test only read: bit 7 6 5 4 3 2 1 bit 0 write: $0018 - $0019 reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0018 - $0019 reserved read: 0 0 0 0 0 0 0 0 write: $001a - $001b device id register ( (table 1-3) ) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001a partidh read: id15 id14 id13 id12 id11 id10 id9 id8 write: $001b partidl read: id7 id6 id5 id4 id3 id2 id1 id0 write: $001c - $001d mmc map 3 of 4 (hcs12 module mapping control, (table 1-4) ) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001c memsiz0 read: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0 write: $001d memsiz1 read: rom_sw1 rom_sw0 0 0 0 0 pag_sw1 pag_sw0 write: $001e - $001e mebi map 2 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001e intcr read: irqe irqen 0 0 0 0 0 0 write:
device user guide ?9s12dt128dgv2/d v02.15 34 freescale semiconductor $001f - $001f int map 2 of 2 (hcs12 interrupt) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001f hprio read: psel7 psel6 psel5 psel4 psel3 psel2 psel1 0 write: $0020 - $0027 reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0020 - $0027 reserved read: 0 0 0 0 0 0 0 0 write: $0028 - $002f bkp (hcs12 breakpoint) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0028 bkpct0 read: bken bkfull bkbdm bktag 0 0 0 0 write: $0029 bkpct1 read: bk0mbh bk0mbl bk1mbh bk1mbl bk0rwe bk0rw bk1rwe bk1rw write: $002a bkp0x read: 0 0 bk0v5 bk0v4 bk0v3 bk0v2 bk0v1 bk0v0 write: $002b bkp0h read: bit 15 14 13 12 11 10 9 bit 8 write: $002c bkp0l read: bit 7 6 5 4 3 2 1 bit 0 write: $002d bkp1x read: 0 0 bk1v5 bk1v4 bk1v3 bk1v2 bk1v1 bk1v0 write: $002e bkp1h read: bit 15 14 13 12 11 10 9 bit 8 write: $002f bkp1l read: bit 7 6 5 4 3 2 1 bit 0 write: $0030 - $0031 mmc map 4 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0030 ppage read: 0 0 pix5 pix4 pix3 pix2 pix1 pix0 write: $0031 reserved read: 0 0 0 0 0 0 0 0 write: $0032 - $0033 mebi map 3 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0032 portk read: bit 7 6 5 4 3 2 1 bit 0 write: $0033 ddrk read: bit 7 6 5 4 3 2 1 bit 0 write:
device user guide ?9s12dt128dgv2/d v02.15 35 freescale semiconductor $0034 - $003f crg (clock and reset generator) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0034 synr read: 0 0 syn5 syn4 syn3 syn2 syn1 syn0 write: $0035 refdv read: 0 0 0 0 refdv3 refdv2 refdv1 refdv0 write: $0036 ctflg test only read: 0 0 0 0 0 0 0 0 write: $0037 crgflg read: rtif porf 0 lockif lock track scmif scm write: $0038 crgint read: rtie 0 0 lockie 0 0 scmie 0 write: $0039 clksel read: pllsel pstp syswai roawai pllwai cwai rtiwai copwai write: $003a pllctl read: cme pllon auto acq 0 pre pce scme write: $003b rtictl read: 0 rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 write: $003c copctl read: wcop rsbck 0 0 0 cr2 cr1 cr0 write: $003d forbyp test only read: 0 0 0 0 0 0 0 0 write: $003e ctctl test only read: 0 0 0 0 0 0 0 0 write: $003f armcop read: 0 0 0 0 0 0 0 0 write: bit 7 6 5 4 3 2 1 bit 0 $0040 - $007f ect (enhanced capture timer 16 bit 8 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0040 tios read: ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 write: $0041 cforc read: 0 0 0 0 0 0 0 0 write: foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 $0042 oc7m read: oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 write: $0043 oc7d read: oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 write: $0044 tcnt (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0045 tcnt (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0046 tscr1 read: ten tswai tsfrz tffca 0 0 0 0 write: $0047 ttov read: tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 write: $0048 tctl1 read: om7 ol7 om6 ol6 om5 ol5 om4 ol4 write: $0049 tctl2 read: om3 ol3 om2 ol2 om1 ol1 om0 ol0 write:
device user guide ?9s12dt128dgv2/d v02.15 36 freescale semiconductor $004a tctl3 read: edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a write: $004b tctl4 read: edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a write: $004c tie read: c7i c6i c5i c4i c3i c2i c1i c0i write: $004d tscr2 read: toi 0 0 0 tcre pr2 pr1 pr0 write: $004e tflg1 read: c7f c6f c5f c4f c3f c2f c1f c0f write: $004f tflg2 read: tof 0 0 0 0 0 0 0 write: $0050 tc0 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0051 tc0 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0052 tc1 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0053 tc1 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0054 tc2 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0055 tc2 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0056 tc3 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0057 tc3 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0058 tc4 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0059 tc4 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $005a tc5 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005b tc5 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $005c tc6 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005d tc6 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $005e tc7 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005f tc7 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0060 pactl read: 0 paen pamod pedge clk1 clk0 paov i pa i write: $0061 paflg read: 0 0 0 0 0 0 paov f paif write: $0062 pacn3 (hi) read: bit 7 6 5 4 3 2 1 bit 0 write: $0040 - $007f ect (enhanced capture timer 16 bit 8 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
device user guide ?9s12dt128dgv2/d v02.15 37 freescale semiconductor $0063 pacn2 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0064 pacn1 (hi) read: bit 7 6 5 4 3 2 1 bit 0 write: $0065 pacn0 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0066 mcctl read: mczi modmc rdmcl 0 0 mcen mcpr1 mcpr0 write: iclat flmc $0067 mcflg read: mczf 0 0 0 polf3 polf2 polf1 polf0 write: $0068 icpar read: 0 0 0 0 pa3en pa2en pa1en pa0en write: $0069 dlyct read: 0 0 0 0 0 0 dly1 dly0 write: $006a icovw read: novw7 novw6 novw5 novw4 novw3 novw2 novw1 novw0 write: $006b icsys read: sh37 sh26 sh15 sh04 tfmod pacmx bufen latq write: $006c reserved read: write: $006d timtst test only read: 0 0 0 0 0 0 tcbyp 0 write: $006e reserved read: write: $006f reserved read: write: $0070 pbctl read: 0 pben 0 0 0 0 pbovi 0 write: $0071 pbflg read: 0 0 0 0 0 0 pbovf 0 write: $0072 pa3h read: bit 7 6 5 4 3 2 1 bit 0 write: $0073 pa2h read: bit 7 6 5 4 3 2 1 bit 0 write: $0074 pa1h read: bit 7 6 5 4 3 2 1 bit 0 write: $0075 pa0h read: bit 7 6 5 4 3 2 1 bit 0 write: $0076 mccnt (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0077 mccnt (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0078 tc0h (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0079 tc0h (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $007a tc1h (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $007b tc1h (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0040 - $007f ect (enhanced capture timer 16 bit 8 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
device user guide ?9s12dt128dgv2/d v02.15 38 freescale semiconductor $007c tc2h (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $007d tc2h (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $007e tc3h (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $007f tc3h (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0080 - $009f atd0 (analog to digital converter 10 bit 8 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0080 atd0ctl0 read: 0 0 0 0 0 0 0 0 write: $0081 atd0ctl1 read: 0 0 0 0 0 0 0 0 write: $0082 atd0ctl2 read: adpu affc awai etrigle etrigp etrig ascie ascif write: $0083 atd0ctl3 read: 0 s8c s4c s2c s1c fifo frz1 frz0 write: $0084 atd0ctl4 read: sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 write: $0085 atd0ctl5 read: djm dsgn scan mult 0 cc cb ca write: $0086 atd0stat0 read: scf 0 etorf fifor 0 cc2 cc1 cc0 write: $0087 reserved read: 0 0 0 0 0 0 0 0 write: $0088 atd0test0 read: 0 0 0 0 0 0 0 0 write: $0089 atd0test1 read: 0 0 0 0 0 0 0 sc write: $008a reserved read: 0 0 0 0 0 0 0 0 write: $008b atd0stat1 read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: $008c reserved read: 0 0 0 0 0 0 0 0 write: $008d atd0dien read: bit 7 6 5 4 3 2 1 bit 0 write: $008e reserved read: 0 0 0 0 0 0 0 0 write: $008f portad0 read: bit7 6 5 4 3 2 1 bit 0 write: $0090 atd0dr0h read: bit15 14 13 12 11 10 9 bit8 write: $0091 atd0dr0l read: bit7 bit6 0 0 0 0 0 0 write: $0040 - $007f ect (enhanced capture timer 16 bit 8 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
device user guide ?9s12dt128dgv2/d v02.15 39 freescale semiconductor $0092 atd0dr1h read: bit15 14 13 12 11 10 9 bit8 write: $0093 atd0dr1l read: bit7 bit6 0 0 0 0 0 0 write: $0094 atd0dr2h read: bit15 14 13 12 11 10 9 bit8 write: $0095 atd0dr2l read: bit7 bit6 0 0 0 0 0 0 write: $0096 atd0dr3h read: bit15 14 13 12 11 10 9 bit8 write: $0097 atd0dr3l read: bit7 bit6 0 0 0 0 0 0 write: $0098 atd0dr4h read: bit15 14 13 12 11 10 9 bit8 write: $0099 atd0dr4l read: bit7 bit6 0 0 0 0 0 0 write: $009a atd0dr5h read: bit15 14 13 12 11 10 9 bit8 write: $009b atd0dr5l read: bit7 bit6 0 0 0 0 0 0 write: $009c atd0dr6h read: bit15 14 13 12 11 10 9 bit8 write: $009d atd0dr6l read: bit7 bit6 0 0 0 0 0 0 write: $009e atd0dr7h read: bit15 14 13 12 11 10 9 bit8 write: $009f atd0dr7l read: bit7 bit6 0 0 0 0 0 0 write: $00a0 - $00c7 pwm (pulse width modulator 8 bit 8 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00a0 pwme read: pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 write: $00a1 pwmpol read: ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 write: $00a2 pwmclk read: pclk7 pclk6 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 write: $00a3 pwmprclk read: 0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 write: $00a4 pwmcae read: cae7 cae6 cae5 cae4 cae3 cae2 cae1 cae0 write: $00a5 pwmctl read: con67 con45 con23 con01 pswai pfrz 0 0 write: $00a6 pwmtst test only read: 0 0 0 0 0 0 0 0 write: $00a7 pwmprsc test only read: 0 0 0 0 0 0 0 0 write: $00a8 pwmscla read: bit 7 6 5 4 3 2 1 bit 0 write: $0080 - $009f atd0 (analog to digital converter 10 bit 8 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
device user guide ?9s12dt128dgv2/d v02.15 40 freescale semiconductor $00a9 pwmsclb read: bit 7 6 5 4 3 2 1 bit 0 write: $00aa pwmscnta test only read: 0 0 0 0 0 0 0 0 write: $00ab pwmscntb test only read: 0 0 0 0 0 0 0 0 write: $00ac pwmcnt0 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $00ad pwmcnt1 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $00ae pwmcnt2 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $00af pwmcnt3 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $00b0 pwmcnt4 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $00b1 pwmcnt5 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $00b2 pwmcnt6 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $00b3 pwmcnt7 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $00b4 pwmper0 read: bit 7 6 5 4 3 2 1 bit 0 write: $00b5 pwmper1 read: bit 7 6 5 4 3 2 1 bit 0 write: $00b6 pwmper2 read: bit 7 6 5 4 3 2 1 bit 0 write: $00b7 pwmper3 read: bit 7 6 5 4 3 2 1 bit 0 write: $00b8 pwmper4 read: bit 7 6 5 4 3 2 1 bit 0 write: $00b9 pwmper5 read: bit 7 6 5 4 3 2 1 bit 0 write: $00ba pwmper6 read: bit 7 6 5 4 3 2 1 bit 0 write: $00bb pwmper7 read: bit 7 6 5 4 3 2 1 bit 0 write: $00bc pwmdty0 read: bit 7 6 5 4 3 2 1 bit 0 write: $00bd pwmdty1 read: bit 7 6 5 4 3 2 1 bit 0 write: $00be pwmdty2 read: bit 7 6 5 4 3 2 1 bit 0 write: $00bf pwmdty3 read: bit 7 6 5 4 3 2 1 bit 0 write: $00c0 pwmdty4 read: bit 7 6 5 4 3 2 1 bit 0 write: $00c1 pwmdty5 read: bit 7 6 5 4 3 2 1 bit 0 write: $00a0 - $00c7 pwm (pulse width modulator 8 bit 8 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
device user guide ?9s12dt128dgv2/d v02.15 41 freescale semiconductor $00c2 pwmdty6 read: bit 7 6 5 4 3 2 1 bit 0 write: $00c3 pwmdty7 read: bit 7 6 5 4 3 2 1 bit 0 write: $00c4 pwmsdn read: pwmif pwmie pwmrstrt pwmlvl 0 pwm7in pwm7inl pwm7ena write: $00c5 reserved read: 0 0 0 0 0 0 0 0 write: $00c6 reserved read: 0 0 0 0 0 0 0 0 write: $00c7 reserved read: 0 0 0 0 0 0 0 0 write: $00c8 - $00cf sci0 (asynchronous serial interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00c8 sci0bdh read: 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 write: $00c9 sci0bdl read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $00ca sci0cr1 read: loops sciswai rsrc m wake ilt pe pt write: $00cb sci0cr2 read: tie tcie rie ilie te re rwu sbk write: $00cc sci0sr1 read: tdre tc rdrf idle or nf fe pf write: $00cd sci0sr2 read: 0 0 0 0 0 brk13 txdir raf write: $00ce sci0drh read: r8 t8 0 0 0 0 0 0 write: $00cf sci0drl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 $00d0 - $00d7 sci1 (asynchronous serial interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00d0 sci1bdh read: 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 write: $00d1 sci1bdl read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $00d2 sci1cr1 read: loops sciswai rsrc m wake ilt pe pt write: $00d3 sci1cr2 read: tie tcie rie ilie te re rwu sbk write: $00d4 sci1sr1 read: tdre tc rdrf idle or nf fe pf write: $00a0 - $00c7 pwm (pulse width modulator 8 bit 8 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
device user guide ?9s12dt128dgv2/d v02.15 42 freescale semiconductor $00d5 sci1sr2 read: 0 0 0 0 0 brk13 txdir raf write: $00d6 sci1drh read: r8 t8 0 0 0 0 0 0 write: $00d7 sci1drl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 $00d8 - $00df spi0 (serial peripheral interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00d8 spi0cr1 read: spie spe sptie mstr cpol cpha ssoe lsbfe write: $00d9 spi0cr2 read: 0 0 0 modfen bidiroe 0 spiswai spc0 write: $00da spi0br read: 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 write: $00db spi0sr read: spif 0 sptef modf 0 0 0 0 write: $00dc reserved read: 0 0 0 0 0 0 0 0 write: $00dd spi0dr read: bit7 6 5 4 3 2 1 bit0 write: $00de reserved read: 0 0 0 0 0 0 0 0 write: $00df reserved read: 0 0 0 0 0 0 0 0 write: $00e0 - $00e7 iic (inter ic bus) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00e0 ibad read: adr7 adr6 adr5 adr4 adr3 adr2 adr1 0 write: $00e1 ibfd read: ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 write: $00e2 ibcr read: iben ibie ms/ sl tx/ rx txak 0 0 ibswai write: rsta $00e3 ibsr read: tcf iaas ibb ibal 0 srw ibif rxak write: $00e4 ibdr read: d7 d6 d5 d4 d3 d2 d1 d 0 write: $00e5 reserved read: 0 0 0 0 0 0 0 0 write: $00e6 reserved read: 0 0 0 0 0 0 0 0 write: $00e7 reserved read: 0 0 0 0 0 0 0 0 write: $00d0 - $00d7 sci1 (asynchronous serial interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
device user guide ?9s12dt128dgv2/d v02.15 43 freescale semiconductor $00e8 - $00ef bdlc (byte level data link controller j1850) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00e8 dlcbcr1 read: imsg clks 0 0 0 0 ie wcm write: $00e9 dlcbsvr read: 0 0 i3 i2 i1 i0 0 0 write: $00ea dlcbcr2 read: smrst dloop rx4xe nbfs teod tsifr tmifr1 tmifr0 write: $00eb dlcbdr read: d7 d6 d5 d4 d3 d2 d1 d0 write: $00ec dlcbard read: 0 rxpol 0 0 bo3 bo2 bo1 bo0 write: $00ed dlcbrsr read: 0 0 r5 r4 r3 r2 r1 r0 write: $00ee dlcscr read: 0 0 0 bdlce 0 0 0 0 write: $00ef dlcbstat read: 0 0 0 0 0 0 0 idle write: $00f0 - $00f7 spi1 (serial peripheral interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00f0 spi1cr1 read: spie spe sptie mstr cpol cpha ssoe lsbfe write: $00f1 spi1cr2 read: 0 0 0 modfen bidiroe 0 spiswai spc0 write: $00f2 spi1br read: 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 write: $00f3 spi1sr read: spif 0 sptef modf 0 0 0 0 write: $00f4 reserved read: 0 0 0 0 0 0 0 0 write: $00f5 spi1dr read: bit7 6 5 4 3 2 1 bit0 write: $00f6 reserved read: 0 0 0 0 0 0 0 0 write: $00f7 reserved read: 0 0 0 0 0 0 0 0 write: $00f8 - $00ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00f8 - $00ff reserved read: 0 0 0 0 0 0 0 0 write:
device user guide ?9s12dt128dgv2/d v02.15 44 freescale semiconductor $0100 - $010f flash control register (fts128k2) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0100 fclkdiv read: fdivld prdiv8 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 write: $0101 fsec read: keyen1 keyen0 nv5 nv4 nv3 nv2 sec1 sec0 write: $0102 ftstmod read: 0 0 0 wrall 0 0 0 0 write: $0103 fcnfg read: cbeie ccie keyacc 0 0 0 bksel1 bksel0 write: $0104 fprot read: fpopen nv6 fphdis fphs1 fphs0 fpldis fpls1 fpls0 write: $0105 fstat read: cbeif ccif pviol accerr 0 blank 0 0 write: $0106 fcmd read: 0 cmdb6 cmdb5 0 0 cmdb2 0 cmdb0 write: $0107 reserved for factory test read: 0 0 0 0 0 0 0 0 write: $0108 faddrhi read: 0 bit 14 13 12 11 10 9 bit 8 write: $0109 faddrlo read: bit 7 6 5 4 3 2 1 bit 0 write: $010a fdatahi read: bit 15 14 13 12 11 10 9 bit 8 write: $010b fdatalo read: bit 7 6 5 4 3 2 1 bit 0 write: $010c - $010f reserved read: 0 0 0 0 0 0 0 0 write: $0110 - $011b eeprom control register (eets2k) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0110 eclkdiv read: edivld prdiv8 ediv5 ediv4 ediv3 ediv2 ediv1 ediv0 write: $0111 reserved read: 0 0 0 0 0 0 0 0 write: $0112 reserved for factory test read: 0 0 0 0 0 0 0 0 write: $0113 ecnfg read: cbeie ccie 0 0 0 0 0 0 write: $0114 eprot read: epopen nv6 nv5 nv4 epdis ep2 ep1 ep0 write: $0115 estat read: cbeif ccif pviol accerr 0 blank 0 0 write: $0116 ecmd read: 0 cmdb6 cmdb5 0 0 cmdb2 0 cmdb0 write: $0117 reserved for factory test read: 0 0 0 0 0 0 0 0 write: $0118 eaddrhi read: 0 0 0 0 0 0 bit 9 bit 8 write:
device user guide ?9s12dt128dgv2/d v02.15 45 freescale semiconductor $0119 eaddrlo read: bit 7 6 5 4 3 2 1 bit 0 write: $011a edatahi read: bit 15 14 13 12 11 10 9 bit 8 write: $011b edatalo read: bit 7 6 5 4 3 2 1 bit 0 write: $011c - $011f reserved for ram control register address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $011c - $011f reserved read: 0 0 0 0 0 0 0 0 write: $0120 - $013f atd1 (analog to digital converter 10 bit 8 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0120 atd1ctl0 read: 0 0 0 0 0 0 0 0 write: $0121 atd1ctl1 read: 0 0 0 0 0 0 0 0 write: $0122 atd1ctl2 read: adpu affc awai etrigle etrigp etrig ascie ascif write: $0123 atd1ctl3 read: 0 s8c s4c s2c s1c fifo frz1 frz0 write: $0124 atd1ctl4 read: sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 write: $0125 atd1ctl5 read: djm dsgn scan mult 0 cc cb ca write: $0126 atd1stat0 read: scf 0 etorf fifor 0 cc2 cc1 cc0 write: $0127 reserved read: 0 0 0 0 0 0 0 0 write: $0128 atd1test0 read: 0 0 0 0 0 0 0 0 write: $0129 atd1test1 read: 0 0 0 0 0 0 0 sc write: $012a reserved read: 0 0 0 0 0 0 0 0 write: $012b atd1stat1 read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: $012c reserved read: 0 0 0 0 0 0 0 0 write: $012d atd1dien read: bit 7 6 5 4 3 2 1 bit 0 write: $012e reserved read: 0 0 0 0 0 0 0 0 write: $012f portad1 read: bit7 6 5 4 3 2 1 bit 0 write: $0110 - $011b eeprom control register (eets2k) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
device user guide ?9s12dt128dgv2/d v02.15 46 freescale semiconductor $0130 atd1dr0h read: bit15 14 13 12 11 10 9 bit8 write: $0131 atd1dr0l read: bit7 bit6 0 0 0 0 0 0 write: $0132 atd1dr1h read: bit15 14 13 12 11 10 9 bit8 write: $0133 atd1dr1l read: bit7 bit6 0 0 0 0 0 0 write: $0134 atd1dr2h read: bit15 14 13 12 11 10 9 bit8 write: $0135 atd1dr2l read: bit7 bit6 0 0 0 0 0 0 write: $0136 atd1dr3h read: bit15 14 13 12 11 10 9 bit8 write: $0137 atd1dr3l read: bit7 bit6 0 0 0 0 0 0 write: $0138 atd1dr4h read: bit15 14 13 12 11 10 9 bit8 write: $0139 atd1dr4l read: bit7 bit6 0 0 0 0 0 0 write: $013a atd1dr5h read: bit15 14 13 12 11 10 9 bit8 write: $013b atd1dr5l read: bit7 bit6 0 0 0 0 0 0 write: $013c atd1dr6h read: bit15 14 13 12 11 10 9 bit8 write: $013d atd1dr6l read: bit7 bit6 0 0 0 0 0 0 write: $013e atd1dr7h read: bit15 14 13 12 11 10 9 bit8 write: $013f atd1dr7l read: bit7 bit6 0 0 0 0 0 0 write: $0140 - $017f can0 (motorola scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0140 can0ctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $0141 can0ctl1 read: cane clksrc loopb listen 0 wupm slpak initak write: $0142 can0btr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0143 can0btr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0144 can0rflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: $0145 can0rier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $0120 - $013f atd1 (analog to digital converter 10 bit 8 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
device user guide ?9s12dt128dgv2/d v02.15 47 freescale semiconductor $0146 can0tflg read: 0 0 0 0 0 txe2 txe1 txe0 write: $0147 can0tier read: 0 0 0 0 0 txeie2 txeie1 txeie0 write: $0148 can0tarq read: 0 0 0 0 0 abtrq2 abtrq1 abtrq0 write: $0149 can0taak read: 0 0 0 0 0 abtak2 abtak1 abtak0 write: $014a can0tbsel read: 0 0 0 0 0 tx2 tx1 tx0 write: $014b can0idac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $014c reserved read: 0 0 0 0 0 0 0 0 write: $014d reserved read: 0 0 0 0 0 0 0 0 write: $014e can0rxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $014f can0txerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0150 - $0153 can0idar0 - can0idar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0154 - $0157 can0idmr0 - can0idmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0158 - $015b can0idar4 - can0idar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $015c - $015f can0idmr4 - can0idmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0160 - $016f can0rxfg read: foreground receive buffer see (table 1-2) write: $0170 - $017f can0txfg read: foreground transmit buffer see (table 1-2) write: table 1-2 detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $xxx0 extended id read: id28 id27 id26 id25 id24 id23 id22 id21 standard id read: id10 id9 id8 id7 id6 id5 id4 id3 canxridr0 write: $xxx1 extended id read: id20 id19 id18 srr=1 ide=1 id17 id16 id15 standard id read: id2 id1 id0 rtr ide=0 canxridr1 write: $xxx2 extended id read: id14 id13 id12 id11 id10 id9 id8 id7 standard id read: canxridr2 write: $xxx3 extended id read: id6 id5 id4 id3 id2 id1 id0 rtr standard id read: canxridr3 write: $xxx4- $xxxb canxrdsr0 - canxrdsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $0140 - $017f can0 (motorola scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
device user guide ?9s12dt128dgv2/d v02.15 48 freescale semiconductor $xxxc canrxdlr read: dlc3 dlc2 dlc1 dlc0 write: $xxxd reserved read: write: $xxxe canxrtsrh read: tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 write: $xxxf canxrtsrl read: tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 write: $xx10 extended id read: id28 id27 id26 id25 id24 id23 id22 id21 canxtidr0 write: standard id read: id10 id9 id8 id7 id6 id5 id4 id3 write: $xx11 extended id read: id20 id19 id18 srr=1 ide=1 id17 id16 id15 canxtidr1 write: standard id read: id2 id1 id0 rtr ide=0 write: $xx12 extended id read: id14 id13 id12 id11 id10 id9 id8 id7 canxtidr2 write: standard id read: write: $xx13 extended id read: id6 id5 id4 id3 id2 id1 id0 rtr canxtidr3 write: standard id read: write: $xx14- $xx1b canxtdsr0 - canxtdsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $xx1c canxtdlr read: dlc3 dlc2 dlc1 dlc0 write: $xx1d conxttbpr read: prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 write: $xx1e canxttsrh read: tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 write: $xx1f canxttsrl read: tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 write: $0180 - $01bf can1 (motorola scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0180 can1ctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $0181 can1ctl1 read: cane clksrc loopb listen 0 wupm slpak initak write: $0182 can1btr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0183 can1btr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0184 can1rflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: table 1-2 detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
device user guide ?9s12dt128dgv2/d v02.15 49 freescale semiconductor $0185 can1rier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $0186 can1tflg read: 0 0 0 0 0 txe2 txe1 txe0 write: $0187 can1tier read: 0 0 0 0 0 txeie2 txeie1 txeie0 write: $0188 can1tarq read: 0 0 0 0 0 abtrq2 abtrq1 abtrq0 write: $0189 can1taak read: 0 0 0 0 0 abtak2 abtak1 abtak0 write: $018a can1tbsel read: 0 0 0 0 0 tx2 tx1 tx0 write: $018b can1idac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $018c reserved read: 0 0 0 0 0 0 0 0 write: $018d reserved read: 0 0 0 0 0 0 0 0 write: $018e can1rxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $018f can1txerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0190 - $0193 can1idar0 - can1idar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0194 - $0197 can1idmr0 - can1idmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0198 - $019b can1idar4 - can1idar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $019c - $019f can1idmr4 - can1idmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $01a0 - $01af can0rxfg read: foreground receive buffer see (table 1-2) write: $01b0 - $01bf can0txfg read: foreground transmit buffer see (table 1-2) write: $01c0 - $01ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $01c0 - $01ff reserved read: 0 0 0 0 0 0 0 0 write: $0200 - $023f reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $020c - $023f reserved read: 0 0 0 0 0 0 0 0 write: $0180 - $01bf can1 (motorola scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
device user guide ?9s12dt128dgv2/d v02.15 50 freescale semiconductor $0240 - $027f pim (port integration module) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0240 ptt read: ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 write: $0241 ptit read: ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 write: $0242 ddrt read: ddrt7 ddrt7 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 write: $0243 rdrt read: rdrt7 rdrt6 rdrt5 rdrt4 rdrt3 rdrt2 rdrt1 rdrt0 write: $0244 pert read: pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 write: $0245 ppst read: ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 write: $0246 reserved read: 0 0 0 0 0 0 0 0 write: $0247 reserved read: 0 0 0 0 0 0 0 0 write: $0248 pts read: pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 write: $0249 ptis read: ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 write: $024a ddrs read: ddrs7 ddrs7 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 write: $024b rdrs read: rdrs7 rdrs6 rdrs5 rdrs4 rdrs3 rdrs2 rdrs1 rdrs0 write: $024c pers read: pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 write: $024d ppss read: ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 write: $024e woms read: woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 write: $024f reserved read: 0 0 0 0 0 0 0 0 write: $0250 ptm read: ptm7 ptm6 ptm5 ptm4 ptm3 ptm2 ptm1 ptm0 write: $0251 ptim read: ptim7 ptim6 ptim5 ptim4 ptim3 ptim2 ptim1 ptim0 write: $0252 ddrm read: ddrm7 ddrm7 ddrm5 ddrm4 ddrm3 ddrm2 ddrm1 ddrm0 write: $0253 rdrm read: rdrm7 rdrm6 rdrm5 rdrm4 rdrm3 rdrm2 rdrm1 rdrm0 write: $0254 perm read: perm7 perm6 perm5 perm4 perm3 perm2 perm1 perm0 write: $0255 ppsm read: ppsm7 ppsm6 ppsm5 ppsm4 ppsm3 ppsm2 ppsm1 ppsm0 write: $0256 womm read: womm7 womm6 womm5 womm4 womm3 womm2 womm1 womm0 write: $0257 modrr read: 0 0 modrr5 modrr4 modrr3 modrr2 modrr1 modrr0 write: $0258 ptp read: ptp7 ptp6 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 write:
device user guide ?9s12dt128dgv2/d v02.15 51 freescale semiconductor $0259 ptip read: ptip7 ptip6 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 write: $025a ddrp read: ddrp7 ddrp7 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 write: $025b rdrp read: rdrp7 rdrp6 rdrp5 rdrp4 rdrp3 rdrp2 rdrp1 rdrp0 write: $025c perp read: perp7 perp6 perp5 perp4 perp3 perp2 perp1 perp0 write: $025d ppsp read: ppsp7 ppsp6 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppss0 write: $025e piep read: piep7 piep6 piep5 piep4 piep3 piep2 piep1 piep0 write: $025f pifp read: pifp7 pifp6 pifp5 pifp4 pifp3 pifp2 pifp1 pifp0 write: $0260 pth read: pth7 pth6 pth5 pth4 pth3 pth2 pth1 pth0 write: $0261 ptih read: ptih7 ptih6 ptih5 ptih4 ptih3 ptih2 ptih1 ptih0 write: $0262 ddrh read: ddrh7 ddrh7 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 write: $0263 rdrh read: rdrh7 rdrh6 rdrh5 rdrh4 rdrh3 rdrh2 rdrh1 rdrh0 write: $0264 perh read: perh7 perh6 perh5 perh4 perh3 perh2 perh1 perh0 write: $0265 ppsh read: ppsh7 ppsh6 ppsh5 ppsh4 ppsh3 ppsh2 ppsh1 ppsh0 write: $0266 pieh read: pieh7 pieh6 pieh5 pieh4 pieh3 pieh2 pieh1 pieh0 write: $0267 pifh read: pifh7 pifh6 pifh5 pifh4 pifh3 pifh2 pifh1 pifh0 write: $0268 ptj read: ptj7 ptj6 0 0 0 0 ptj1 ptj0 write: $0269 ptij read: ptij7 ptij6 0 0 0 0 ptij1 ptij0 write: $026a ddrj read: ddrj7 ddrj7 0 0 0 0 ddrj1 ddrj0 write: $026b rdrj read: rdrj7 rdrj6 0 0 0 0 rdrj1 rdrj0 write: $026c perj read: perj7 perj6 0 0 0 0 perj1 perj0 write: $026d ppsj read: ppsj7 ppsj6 0 0 0 0 ppsj1 ppsj0 write: $026e piej read: piej7 piej6 0 0 0 0 piej1 piej0 write: $026f pifj read: pifj7 pifj6 0 0 0 0 pifj1 pifj0 write: $0270 - $027f reserved read: 0 0 0 0 0 0 0 0 write: $0240 - $027f pim (port integration module) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
device user guide ?9s12dt128dgv2/d v02.15 52 freescale semiconductor $0280 - $02bf can4 (motorola scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0280 can4ctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $0281 can4ctl1 read: cane clksrc loopb listen 0 wupm slpak initak write: $0282 can4btr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0283 can4btr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0284 can4rflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: $0285 can4rier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $0286 can4tflg read: 0 0 0 0 0 txe2 txe1 txe0 write: $0287 can4tier read: 0 0 0 0 0 txeie2 txeie1 txeie0 write: $0288 can4tarq read: 0 0 0 0 0 abtrq2 abtrq1 abtrq0 write: $0289 can4taak read: 0 0 0 0 0 abtak2 abtak1 abtak0 write: $028a can4tbsel read: 0 0 0 0 0 tx2 tx1 tx0 write: $028b can4idac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $028c reserved read: 0 0 0 0 0 0 0 0 write: $028d reserved read: 0 0 0 0 0 0 0 0 write: $028e can4rxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $028f can4txerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0290 - $0293 can0idar0 - can0idar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0294 - $0297 can0idmr0 - can0idmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0298 - $029b can0idar4 - can0idar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $029c - $029f can0idmr4 - can0idmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 $02a0 - $02af can4rxfg read: foreground receive buffer see (table 1-2) write: $02b0 - $02bf can4txfg read: foreground transmit buffer see (table 1-2) write:
device user guide ?9s12dt128dgv2/d v02.15 53 freescale semiconductor $02c0 - $02ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $02c0 - $02ff reserved read: 0 0 0 0 0 0 0 0 write: $0300 - $035f byte?ght address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0300 bfmcr read: initrq master alarm slpak slprq wpulse sswai initak write: $0301 bffsizr read: 0 0 0 fsiz4 fsiz3 fsiz2 fsiz1 fsiz0 write: $0302 bftcr1 read: twx0t7 twx0t6 twx0t5 twx0t4 twx0t3 twx0t2 twx0t1 twx0t0 write: $0303 bftcr2 read: twx0r7 twx0r6 twx0r5 twx0r4 twx0r3 twx0r2 twx0r1 twx0r0 write: $0304 bftcr3 read: twx0d7 twx0d6 twx0d5 twx0d4 twx0d3 twx0d2 twx0d1 twx0d0 write: $0305 reserved read: 0 0 0 0 0 0 0 0 write: $0306 bfrisr read: rcvfif rxif synaif synnif slmmif 0 xsynif optdf write: $0307 bfgisr read: txif ovrnif errif syneif synlif illpif lockif wakeif write: $0308 bfrier read: rcvfie rxie synaie synnie slmmie 0 xsynie 0 write: $0309 bfgier read: txie ovrnie errie syneie synlie illpie lockie wakeie write: $030a bfrivec read: 0 0 0 0 rivec3 rivec2 rivec1 rivec0 write: $030b bftivec read: 0 0 0 0 tivec3 tivec2 tivec1 tivec0 write: $030c bffidac read: fidac7 fidac6 fidac5 fidac4 fidac3 fidac2 fidac1 fidac0 write: $030d bffidmr read: fidmr7 fidmr6 fidmr5 fidmr4 fidmr3 fidmr2 fidmr1 fidmr0 write: $030e bfmvr read: mvr7 mvr6 mvr5 mvr4 mvr3 mvr2 mvr1 mvr0 write: $030f reserved read: 0 0 0 0 0 0 0 0 write: $0310 bfpctlbf read: pmeren 0 pslmen perren proken psynen 0 bfen write: $0311 reserved read: 0 0 0 0 0 0 0 0 write: $0312 bfbuflock read: 0 0 0 0 0 0 txbufl ock rxbufl ock write: $0313 reserved read: 0 0 0 0 0 0 0 0 write: $0314 bffidrj read: fidrj7 fidrj6 fidrj5 fidrj4 fidrj3 fidrj2 fidrj1 fidrj0 write:
device user guide ?9s12dt128dgv2/d v02.15 54 freescale semiconductor $0315 bffidrmr read: fidrmr 7 fidrmr 6 fidrmr 5 fidrmr 5 fidrmr 4 fidrmr 3 fidrmr 2 fidrmr 1 write: $0316 reserved read: 0 0 0 0 0 0 0 0 write: $0317 reserved read: 0 0 0 0 0 0 0 0 write: $0318 reserved read: 0 0 0 0 0 0 0 0 write: $0319 reserved read: 0 0 0 0 0 0 0 0 write: $031a reserved read: 0 0 0 0 0 0 0 0 write: $031b reserved read: 0 0 0 0 0 0 0 0 write: $031c reserved read: 0 0 0 0 0 0 0 0 write: $031d reserved read: 0 0 0 0 0 0 0 0 write: $031e reserved read: 0 0 0 0 0 0 0 0 write: $031f reserved read: 0 0 0 0 0 0 0 0 write: $0320 bftident read: id7 id6 id5 id4 id3 id2 id1 id0 write: $0321 bftlen read: len3 len2 len1 len0 write: $0322 - $032d bftdata0- bftdata11 read: data7 data6 data5 data4 data3 data2 data1 data0 write: $032e - $032f reserved read: write: $0330 bfrident read: id7 id6 id5 id4 id3 id2 id1 id0 write: $0331 bfrlen read: len3 len2 len1 len0 write: $0332 - $033d bfrdata0- bfrdata11 read: data7 data6 data5 data4 data3 data2 data1 data 0 write: $033e- $033f reserved read: write: $0340 bffident read: id7 id6 id5 id4 id3 id2 id1 id0 write: $0341 bfflen read: len3 len2 len1 len0 write: $0342 - $034d bffdata0- bffdata11 read: data 7 data6 data5 data4 data3 data2 data1 data0 write: $034e - $034f reserved read: write: $0350 - $035f bfbufctl0 - bfbufctl15 read: iflg iena lock abtak abtrq 0 0 cfg write: $0300 - $035f byte?ght address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
device user guide ?9s12dt128dgv2/d v02.15 55 freescale semiconductor 1.6 part id assignments the part id is located in two 8-bit registers partidh and partidl (addresses $001a and $001b after reset). the read-only value is a unique part id for each revision of the chip. (table 1-3) shows the assigned part id number. the device memory sizes are located in two 8-bit registers memsiz0 and memsiz1 (addresses $001c and $001d after reset). table 1-4 shows the read-only values of these registers. refer to hcs12 module mapping control (mmc) block guide for further details. $0360 - $03ff reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0360 - $03ff reserved read: 0 0 0 0 0 0 0 0 write: table 1-3 assigned part id numbers device mask set number part id 1 notes : 1. the coding is as follows: bit 15-12: major family identifier bit 11-8: minor family identifier bit 7-4: major mask set revision number including fab transfers bit 3-0: minor - non full - mask set revision mc9s12dt128 1l40k $0111 mc9s12dt128 3l40k $0113 mc9s12dt128 4l40k $0114 mc9s12dt128 0l94r $0110 mc9s12dt128 1l59w $0115 mc9s12dt128 5l40k $0115 table 1-4 memory size registers register name value memsiz0 $13 memsiz1 $80
device user guide ?9s12dt128dgv2/d v02.15 56 freescale semiconductor
device user guide ?9s12dt128dgv2/d v02.15 57 freescale semiconductor section 2 signal description this section describes signals that connect off-chip. it includes a pinout diagram, a table of signal properties, and detailed discussion of signals. it is built from the signal description sections of the block user guides of the individual ip blocks on the device. 2.1 device pinout the mc9s12dt128 and its derivatives are available in a 112-pin low profile quad flat pack (lqfp) and in a 80-pin quad flat pack (qfp). most pins perform two or more functions, as described in the signal descriptions. figure 2-1 , figure 2-2 , and figure 2-3 show the pin assignments for different packages.
device user guide ?9s12dt128dgv2/d v02.15 58 freescale semiconductor figure 2-1 pin assignments 112 lqfp for mc9s12dt128e, mc9s12dt128, mc9s12dg128e, mc9s12dg128, mc9s12dj128e, mc9s12dj128, mc9s12db128 mc9s12a128, sc515846, sc515847, sc515848, sc515849, sc101161dt, sc101161dg, sc101161dj, sc102202, sc102203, sc102204, and sc102205 vrh vdda pad15/an15/etrig1 pad07/an07/etrig0 pad14/an14 pad06/an06 pad13/an13 pad05/an05 pad12/an12 pad04/an04 pad11/an11 pad03/an03 pad10/an10 pad02/an02 pad09/an09 pad01/an01 pad08/an08 pad00/an00 vss2 vdd2 pa7/addr15/data15 pa6/addr14/data14 pa5/addr13/data13 pa4/addr12/data12 pa3/addr11/data11 pa2/addr10/data10 pa1/addr9/data9 pa0/addr8/data8 pp4/kwp4/pwm4 pp5/kwp5/pwm5 pp6/kwp6/pwm6 pp7/kwp7/pwm7 pk7/ ecs/romctl vddx vssx pm0/rxcan0/rxb pm1/txcan0/txb pm2/rx_bf/rxcan1/rxcan0/miso0 pm3/tx_bf/txcan1/txcan0/ ss0 pm4/bf_psyn/rxcan0/rxcan4/mosi0 pm5/bf_prok/txcan0/txcan4/sck0 pj6/kwj6/rxcan4/sda/rxcan0 pj7/kwj7/txcan4/scl/txcan0 vregen ps7/ ss0 ps6/sck0 ps5/mosi0 ps4/miso0 ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 pm6/bf_perr/rxcan4 pm7/bf_pslm/txcan4 vssa vrl ss1/pwm3/kwp3/pp3 sck1/pwm2/kwp2/pp2 mosi1/pwm1/kwp1/pp1 miso1/pwm0/kwp0/pp0 xaddr17/pk3 xaddr16/pk2 xaddr15/pk1 xaddr14/pk0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vdd1 vss1 ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 xaddr19/pk5 xaddr18/pk4 kwj1/pj1 kwj0/pj0 modc/ t a ghi/bkgd addr0/data0/pb0 addr1/data1/pb1 addr2/data2/pb2 addr3/data3/pb3 addr4/data4/pb4 addr5/data5/pb5 addr6/data6/pb6 addr7/data7/pb7 kwh7/ph7 kwh6/ph6 kwh5/ph5 kwh4/ph4 xclks/noacc/pe7 modb/ipipe1/pe6 moda/ipipe0/pe5 eclk/pe4 vssr vddr reset vddpll xfc vsspll extal xtal test ss1/kwh3/ph3 sck1/kwh2/ph2 mosi1/kwh1/ph1 miso1/kwh0/ph0 lstrb/ t a glo/pe3 r/ w/pe2 irq/pe1 xirq/pe0 signals shown in bold are not available on all the 80 pin package options mc9s12dt128e, mc9s12dt128, mc9s12dg128e, mc9s12dg128, mc9s12dj128e, mc9s12dj128, mc9s12db128, mc9s12a128, sc515846, sc515847, sc515848, sc515849, sc101161dt, sc101161dg, sc101161dj, sc102202, sc102203, sc102204, sc102205 112lqfp 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 signals shown in bold-italics are not available on the mc9s12dj128e, mc9s12dj128, mc9s12dg128e, mc9s12dg128, mc9s12a128, signals shown in italics are not available on the mc9s12db128, sc515846, and sc102202 80 pin package options sc515847, sc515848, sc101161dg, sc101161dj, sc102203, and sc102204 80 pin package options
device user guide ?9s12dt128dgv2/d v02.15 59 freescale semiconductor figure 2-2 pin assignments in 80 qfp for mc9s12dg128e, mc9s12dg128, mc9s12dj128e, mc9s12dj128, mc9s12a128, sc515847, sc515848, sc101161dg, sc101161dj, sc102203, and sc102204 bondout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 mc9s12dg128e, mc9s12dg128, mc9s12dj128e, mc9s12dj128, mc9s12a128, sc515847, sc515848, sc101161dg, sc101161dj, sc102203, sc102204 80 qfp vrh vdda pad07/an07/etrig0 pad06/an06 pad05/an05 pad04/an04 pad03/an03 pad02/an02 pad01/an01 pad00/an00 vss2 vdd2 pa7/addr15/data15 pa6/addr14/data14 pa5/addr13/data13 pa4/addr12/data12 pa3/addr11/data11 pa2/addr10/data10 pa1/addr9/data9 pa0/addr8/data8 pp4/kwp4/pwm4 pp5/kwp5/pwm5 pp7/kwp7/pwm7 vddx vssx pm0/rxcan0/rxb pm1/txcan0/txb pm2/rxcan1/rxcan0/miso0 pm3/txcan1/txcan0/ ss0 pm4/rxcan0/rxcan4/mosi0 pm5/txcan0/txcan4/sck0 pj6/kwj6/rxcan4/sda/rxcan0 pj7/kwj7/txcan4/scl/txcan0 vregen ps3/txd1 ps2//rxd1 ps1/txd0 ps0/rxd0 vssa vrl ss1/pwm3/kwp3/pp3 sck1/pwm2/kwp2/pp2 mosi1/pwm1/kwp1/pp1 miso1/pwm0/kwp0/pp0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vdd1 vss1 ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 modc/ t a ghi/bkgd addr0/data0/pb0 addr1/data1/pb1 addr2/data2/pb2 addr3/data3/pb3 addr4/data4/pb4 addr5/data5/pb5 addr6/data6/pb6 addr7/data7/pb7 xclks/noacc/pe7 modb/ipipe1/pe6 moda/ipipe0/pe5 eclk/pe4 vssr vddr reset vddpll xfc vsspll extal xtal test lstrb/ t a glo/pe3 r/ w/pe2 irq/pe1 xirq/pe0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
device user guide ?9s12dt128dgv2/d v02.15 60 freescale semiconductor figure 2-3 pin assignments in 80 qfp for mc9s12db128, sc515846, and sc102202 bondout 2.2 signal properties summary (table 2-1) summarizes the pin functionality. signals shown in bold are not available on all the 80-pin package options. signals shown in bold-italics are not available on the mc9s12dg128e, mc9s12dg128, mc9s12dj128e, mc9s12dj128, mc9s12a128, sc515847, sc515848, sc101161dg, sc101161dj, sc102203, and sc102204 80-pin package options. signals shown in italics are not available on mc9s12db128, sc515846, and sc102202 80-pin package options. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 mc9s12db128, sc515846, sc102202 80 qfp vrh vdda pad07/an07/etrig0 pad06/an06 pad05/an05 pad04/an04 pad03/an03 pad02/an02 pad01/an01 pad00/an00 vss2 vdd2 pa7/addr15/data15 pa6/addr14/data14 pa5/addr13/data13 pa4/addr12/data12 pa3/addr11/data11 pa2/addr10/data10 pa1/addr9/data9 pa0/addr8/data8 pp4/kwp4/pwm4 pp5/kwp5/pwm5 pp7/kwp7/pwm7 vddx vssx pm2/rx_bf pm3/tx_bf pm4/bf_psyn pm5/bf_prok vregen ps7/ ss0 ps6/sck0 ps5/mosi0 ps4/miso0 ps1/txd0 ps0/rxd0 pm6/bf_perr pm7/bf_pslm vssa vrl ss1/pwm3/kwp3/pp3 sck1/pwm2/kwp2/pp2 mosi1/pwm1/kwp1/pp1 miso1/pwm0/kwp0/pp0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vdd1 vss1 ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 modc/ t a ghi/bkgd addr0/data0/pb0 addr1/data1/pb1 addr2/data2/pb2 addr3/data3/pb3 addr4/data4/pb4 addr5/data5/pb5 addr6/data6/pb6 addr7/data7/pb7 xclks/noacc/pe7 modb/ipipe1/pe6 moda/ipipe0/pe5 eclk/pe4 vssr vddr reset vddpll xfc vsspll extal xtal test lstrb/ t a glo/pe3 r/ w/pe2 irq/pe1 xirq/pe0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
device user guide ?9s12dt128dgv2/d v02.15 61 freescale semiconductor table 2-1 signal properties pin name function 1 pin name function 2 pin name function 3 pin name function 4 pin name function 5 powered by internal pull resistor description ctrl reset state extal vddpll na na oscillator pins xtal vddpll na na reset vddr none none external reset test n.a. none none test input vregen vddx na na voltage regulator enable input xfc vddpll na na pll loop filter bkgd t a ghi modc vddr always up up background debug, tag high, mode input pad[15] an1[7] etrig1 vdda none none port ad input, analog inputs, external trigger input (atd1) pad[14:8] an1[6:0] vdda none none port ad input, analog inputs (atd1) pad[7] an0[7] etrig0 vdda none none port ad input, analog inputs, external trigger input (atd0) pad[6:0] an0[6:0] vdda none none port ad input, analog inputs (atd0) pa[7:0] addr[15:8]/ data[15:8] vddr pucr/ pupae disabled port a i/o, multiplexed address/data pb[7:0] addr[7:0]/ data[7:0] vddr pucr/ pupbe disabled port b i/o, multiplexed address/data pe7 noacc xclks vddr pucr/ pupee mode depen- dant 1 port e i/o, access, clock select pe6 ipipe1 modb vddr while reset pin low: down port e i/o, pipe status, mode input pe5 ipipe0 moda vddr port e i/o, pipe status, mode input pe4 eclk vddr pucr/ pupee mode depen- dant 1 port e i/o, bus clock output pe3 lstrb t a glo vddr port e i/o, byte strobe, tag low pe2 r/ w vddr port e i/o, r/ w in expanded modes pe1 irq vddr up port e input, maskable interrupt pe0 xirq vddr port e input, non maskable interrupt ph7 kwh7 --- vddr perh/ ppsh disabled port h i/o, interrupt
device user guide ?9s12dt128dgv2/d v02.15 62 freescale semiconductor ph6 kwh6 --- vddr perh/ ppsh disabled port h i/o, interrupt ph5 kwh5 --- vddr perh/ ppsh disabled port h i/o, interrupt ph4 kwh4 --- vddr perh/ ppsh disabled port h i/o, interrupt ph3 kwh3 ss1 vddr perh/ ppsh disabled port h i/o, interrupt, ss of spi1 ph2 kwh2 sck1 vddr perh/ ppsh disabled port h i/o, interrupt, sck of spi1 ph1 kwh1 mosi1 vddr perh/ ppsh disabled port h i/o, interrupt, mosi of spi1 ph0 kwh0 miso1 vddr perh/ ppsh disabled port h i/o, interrupt, miso of spi1 pj7 kwj7 txcan4 scl txcan0 vddx perj/ ppsj up port j i/o, interrupt, tx of can4, scl of iic pj6 kwj6 rxcan4 sda rxcan0 vddx perj/ ppsj up port j i/o, interrupt, rx of can4, sda of iic pj[1:0] kwj[1:0] vddx perj/ ppsj up port j i/o, interrupts pk7 ecs romctl vddx pucr/ pupke up port k i/o, emulation chip select, rom control pk[5:0] xaddr[19: 14] vddx pucr/ pupke up port k i/o, extended addresses pm7 bf_pslm txcan4 vddx perm/ ppsm disabled port m i/o, bf slot mismatch pulse, tx of can4 pm6 bf_perr rxcan4 vddx perm/ ppsm disabled port m i/o, bf illegal pulse/message format error pulse, rx of can4 pm5 bf_prok txcan0 txcan4 sck0 vddx perm/ ppsm disabled port m i/o, bf reception ok pulse, tx of can0, can4, sck of spi0 pm4 bf_psyn rxcan0 rxcan4 mosi0 vddx perm/ ppsm disabled port m i/o, bf sync pulse (rx/tx) ok pulse o/p, rx of can0, can4, mosi of spi0 pm3 tx_bf txcan1 txcan0 ss0 vddx perm/ ppsm disabled port m i/o, tx of bf, can1, can0, ss of spi0 pm2 rx_bf rxcan1 rxcan0 miso0 vddx perm/ ppsm disabled port m i/o, rx of bf, can1, can0, miso of spi0 pin name function 1 pin name function 2 pin name function 3 pin name function 4 pin name function 5 powered by internal pull resistor description ctrl reset state
device user guide ?9s12dt128dgv2/d v02.15 63 freescale semiconductor pm1 txcan0 txb vddx perm/ ppsm disabled port m i/o, tx of can0, rx of bdlc pm0 rxcan0 rxb vddx perm/ ppsm disabled port m i/o, rx of can0, rx of bdlc pp7 kwp7 pwm7 vddx perp/ ppsp disabled port p i/o, interrupt, channel 7 of pwm pp6 kwp6 pwm6 vddx perp/ ppsp disabled port p i/o, interrupt, channel 6 of pwm pp5 kwp5 pwm5 vddx perp/ ppsp disabled port p i/o, interrupt, channel 5 of pwm pp4 kwp4 pwm4 vddx perp/ ppsp disabled port p i/o, interrupt, channel 4 of pwm pp3 kwp3 pwm3 ss1 vddx perp/ ppsp disabled port p i/o, interrupt, channel 3 of pwm, ss of spi1 pp2 kwp2 pwm2 sck1 vddx perp/ ppsp disabled port p i/o, interrupt, channel 2 of pwm, sck of spi1 pp1 kwp1 pwm1 mosi1 vddx perp/ ppsp disabled port p i/o, interrupt, channel 1 of pwm, mosi of spi1 pp0 kwp0 pwm0 miso1 vddx perp/ ppsp disabled port p i/o, interrupt, channel 0 of pwm, miso2 of spi1 ps7 ss0 vddx pers/ ppss up port s i/o, ss of spi0 ps6 sck0 vddx pers/ ppss up port s i/o, sck of spi0 ps5 mosi0 vddx pers/ ppss up port s i/o, mosi of spi0 ps4 miso0 vddx pers/ ppss up port s i/o, miso of spi0 ps3 txd1 vddx pers/ ppss up port s i/o, txd of sci1 ps2 rxd1 vddx pers/ ppss up port s i/o, rxd of sci1 ps1 txd0 vddx pers/ ppss up port s i/o, txd of sci0 ps0 rxd0 vddx pers/ ppss up port s i/o, rxd of sci0 pt[7:0] ioc[7:0] vddx pert/ ppst disabled port t i/o, timer channels notes : 1. refer to pear register description in hcs12 multiplexed external bus interface (mebi) block guide. pin name function 1 pin name function 2 pin name function 3 pin name function 4 pin name function 5 powered by internal pull resistor description ctrl reset state
device user guide ?9s12dt128dgv2/d v02.15 64 freescale semiconductor 2.3 detailed signal descriptions 2.3.1 extal, xtal ?oscillator pins extal and xtal are the crystal driver and external clock pins. on reset all the device clocks are derived from the extal input frequency. xtal is the crystal output. 2.3.2 reset ?external reset pin an active low bidirectional control signal, it acts as an input to initialize the mcu to a known start-up state, and an output when an internal mcu function causes a reset. 2.3.3 test ?test pin this input only pin is reserved for test. note: the test pin must be tied to vss in all applications. 2.3.4 xfc ?pll loop filter pin pll loop filter. please ask your freescale representative for the interactive application note to compute pll loop filter elements. any current leakage on this pin must be avoided. figure 2-4 pll loop filter connections 2.3.5 bkgd / taghi / modc ?background debug, tag high, and mode pin the bkgd/ taghi /modc pin is used as a pseudo-open-drain pin for the background debug communication. in mcu expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of e-clock tags the high half of the instruction word being read into the instruction queue. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modc bit at the rising edge of reset . this pin has a permanently enabled pull-up device. mcu xfc r c s c p vddpll vddpll
device user guide ?9s12dt128dgv2/d v02.15 65 freescale semiconductor 2.3.6 pad[15] / an1[7] / etrig1 ?port ad input pin [15] pad15 is a general purpose input pin and analog input of the analog to digital converter atd1. it can act as an external trigger input for the atd1. 2.3.7 pad[14:8] / an1[6:0] ?port ad input pins [14:8] pad14 - pad8 are general purpose input pins and analog inputs of the analog to digital converter atd1. 2.3.8 pad[7] / an0[7] / etrig0 ?port ad input pin [7] pad7 is a general purpose input pin and analog input of the analog to digital converter atd0. it can act as an external trigger input for the atd0. 2.3.9 pad[6:0] / an0[6:0] ?port ad input pins [6:0] pad6 - pad8 are general purpose input pins and analog inputs of the analog to digital converter atd0. 2.3.10 pa[7:0] / addr[15:8] / data[15:8] ?port a i/o pins pa7-pa0 are general purpose input or output pins. in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. 2.3.11 pb[7:0] / addr[7:0] / data[7:0] ?port b i/o pins pb7-pb0 are general purpose input or output pins. in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. 2.3.12 pe7 / noacc / xclks ?port e i/o pin 7 pe7 is a general purpose input or output pin. during mcu expanded modes of operation, the noacc signal, when enabled, is used to indicate that the current bus cycle is an unused or ?ree?cycle. this signal will assert when the cpu is not using the bus. the xclks is an input signal which controls whether a crystal in combination with the internal colpitts (low power) oscillator is used or whether pierce oscillator/external clock circuitry is used. the state of this pin is latched at the rising edge of reset . if the input is a logic low the extal pin is configured for an external clock drive. if input is a logic high an oscillator circuit is configured on extal and xtal. since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is an oscillator circuit on extal and xtal.
device user guide ?9s12dt128dgv2/d v02.15 66 freescale semiconductor figure 2-5 colpitts oscillator connections (pe7=1) figure 2-6 pierce oscillator connections (pe7=0) figure 2-7 external clock connections (pe7=0) mcu c 2 extal xtal crystal or vsspll ceramic resonator c 1 c dc * * due to the nature of a translated ground colpitts oscillator a dc voltage bias is applied to the crystal bias conditions and recommended capacitor value c dc . please contact the crystal manufacturer for crystal dc mcu extal xtal r s * r b vsspll crystal or ceramic resonator c 2 c 1 * rs can be zero (shorted) when used with higher frequency crystals. refer to manufacturer? data. mcu extal xtal cmos-compatible external oscillato r not connected (vddpll-level)
device user guide ?9s12dt128dgv2/d v02.15 67 freescale semiconductor 2.3.13 pe6 / modb / ipipe1 ?port e i/o pin 6 pe6 is a general purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modb bit at the rising edge of reset . this pin is shared with the instruction queue tracking signal ipipe1. this pin is an input with a pull-down device which is only active when reset is low. 2.3.14 pe5 / moda / ipipe0 ?port e i/o pin 5 pe5 is a general purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the moda bit at the rising edge of reset . this pin is shared with the instruction queue tracking signal ipipe0. this pin is an input with a pull-down device which is only active when reset is low. 2.3.15 pe4 / eclk ?port e i/o pin 4 pe4 is a general purpose input or output pin. it can be configured to drive the internal bus clock eclk. eclk can be used as a timing reference. 2.3.16 pe3 / lstrb / taglo ?port e i/o pin 3 pe3 is a general purpose input or output pin. in mcu expanded modes of operation, lstrb can be used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, taglo is used to tag the low half of the instruction word being read into the instruction queue. 2.3.17 pe2 / r/ w port e i/o pin 2 pe2 is a general purpose input or output pin. in mcu expanded modes of operations, this pin drives the read/write output signal for the external bus. it indicates the direction of data on the external bus. 2.3.18 pe1 / irq ?port e input pin 1 pe1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. 2.3.19 pe0 / xirq ?port e input pin 0 pe0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. 2.3.20 ph7 / kwh7 ?port h i/o pin 7 ph7 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode.
device user guide ?9s12dt128dgv2/d v02.15 68 freescale semiconductor 2.3.21 ph6 / kwh6 ?port h i/o pin 6 ph6 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. 2.3.22 ph5 / kwh5 ?port h i/o pin 5 ph5 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. 2.3.23 ph4 / kwh4 ?port h i/o pin 2 ph4 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. 2.3.24 ph3 / kwh3 / ss1 ?port h i/o pin 3 ph3 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as slave select pin ss of the serial peripheral interface 1 (spi1). 2.3.25 ph2 / kwh2 / sck1 ?port h i/o pin 2 ph2 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as serial clock pin sck of the serial peripheral interface 1 (spi1). 2.3.26 ph1 / kwh1 / mosi1 ?port h i/o pin 1 ph1 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 1 (spi1). 2.3.27 ph0 / kwh0 / miso1 ?port h i/o pin 0 ph0 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as master input (during master mode) or slave output (during slave mode) pin miso of the serial peripheral interface 1 (spi1). 2.3.28 pj7 / kwj7 / txcan4 / scl / txcan0 ?port j i/o pin 7 pj7 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as the transmit pin txcan for the motorola scalable controller area network controller 0 or 4 (can0, can4) or the serial clock pin scl of the iic module.
device user guide ?9s12dt128dgv2/d v02.15 69 freescale semiconductor 2.3.29 pj6 / kwj6 / rxcan4 / sda / rxcan0 ?port j i/o pin 6 pj6 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as the receive pin rxcan for the motorola scalable controller area network controller 0 or 4 (can0, can4) or the serial data pin sda of the iic module. 2.3.30 pj[1:0] / kwj[1:0] ?port j i/o pins [1:0] pj1 and pj0 are general purpose input or output pins. they can be configured to generate an interrupt causing the mcu to exit stop or wait mode. 2.3.31 pk7 / ecs / romctl ?port k i/o pin 7 pk7 is a general purpose input or output pin. during mcu expanded modes of operation, this pin is used as the emulation chip select output ( ecs ). while configurating mcu expanded modes, this pin is used to enable the flash eeprom memory in the memory map (romctl). at the rising edge of reset , the state of this pin is latched to the romon bit. for a complete list of modes refer to 4.2 chip configuration summary . 2.3.32 pk[5:0] / xaddr[19:14] ?port k i/o pins [5:0] pk5-pk0 are general purpose input or output pins. in mcu expanded modes of operation, these pins provide the expanded address xaddr[19:14] for the external bus. 2.3.33 pm7 / bf_pslm / txcan4 ?port m i/o pin 7 pm7 is a general purpose input or output pin. it can be configured as the slot mismatch output pulse pin of byteflight. it can be configured as the transmit pin txcan of the motorola scalable controller area network controllers 4 (can4). 2.3.34 pm6 / bf_perr / rxcan4 ?port m i/o pin 6 pm6 is a general purpose input or output pin. it can be configured as the illegal pulse or message format error output pulse pin of byteflight. it can be configured as the receive pin rxcan of the motorola scalable controller area network controllers 4 (can4). 2.3.35 pm5 / bf_prok / txcan0 / txcan4 / sck0 ?port m i/o pin 5 pm5 is a general purpose input or output pin. it can be configured as the reception ok output pulse pin of byteflight. it can be configured as the transmit pin txcan of the motorola scalable controller area network controllers 0 or 4 (can0 or can4). it can be configured as the serial clock pin sck of the serial peripheral interface 0 (spi0).
device user guide ?9s12dt128dgv2/d v02.15 70 freescale semiconductor 2.3.36 pm4 / bf_psyn / rxcan0 / rxcan4/ mosi0 ?port m i/o pin 4 pm4 is a general purpose input or output pin. it can be configured as the correct synchronisation pulse reception/transmission output pulse pin of byteflight. it can be configured as the receive pin rxcan of the motorola scalable controller area network controllers 0 or 4 (can0 or can4). it can be configured as the master output (during master mode) or slave input pin (during slave mode) mosi for the serial peripheral interface 0 (spi0). 2.3.37 pm3 / tx_bf / txcan1 / txcan0 / ss0 ?port m i/o pin 3 pm3 is a general purpose input or output pin. it can be configured as the transmit pintx_bf of byteflight. it can be configured as the transmit pin txcan of the motorola scalable controller area network controllers 1 or 0 (can1 or can0). it can be configured as the slave select pin ss of the serial peripheral interface 0 (spi0). 2.3.38 pm2 / rx_bf / rxcan1 / rxcan0 / miso0 ?port m i/o pin 2 pm2 is a general purpose input or output pin. it can be configured as the receive pin rx_bf of byteflight. it can be configured as the receive pin rxcan of the motorola scalable controller area network controllers 1 or 0 (can1 or can0). it can be configured as the master input (during master mode) or slave output pin (during slave mode) miso for the serial peripheral interface 0 (spi0). 2.3.39 pm1 / txcan0 / txb ?port m i/o pin 1 pm1 is a general purpose input or output pin. it can be configured as the transmit pin txcan of the motorola scalable controller area network controller 0 (can0). it can be configured as the transmit pin txb of the bdlc. 2.3.40 pm0 / rxcan0 / rxb ?port m i/o pin 0 pm0 is a general purpose input or output pin. it can be configured as the receive pin rxcan of the motorola scalable controller area network controller 0 (can0). it can be configured as the receive pin rxb of the bdlc. 2.3.41 pp7 / kwp7 / pwm7 ?port p i/o pin 7 pp7 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 7 output. 2.3.42 pp6 / kwp6 / pwm6 ?port p i/o pin 6 pp6 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 6 output.
device user guide ?9s12dt128dgv2/d v02.15 71 freescale semiconductor 2.3.43 pp5 / kwp5 / pwm5 ?port p i/o pin 5 pp5 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 5 output. 2.3.44 pp4 / kwp4 / pwm4 ?port p i/o pin 4 pp4 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 4 output. 2.3.45 pp3 / kwp3 / pwm3 / ss1 ?port p i/o pin 3 pp3 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 3 output. it can be configured as slave select pin ss of the serial peripheral interface 1 (spi1). 2.3.46 pp2 / kwp2 / pwm2 / sck1 ?port p i/o pin 2 pp2 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 2 output. it can be configured as serial clock pin sck of the serial peripheral interface 1 (spi1). 2.3.47 pp1 / kwp1 / pwm1 / mosi1 ?port p i/o pin 1 pp1 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 1 output. it can be configured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 1 (spi1). 2.3.48 pp0 / kwp0 / pwm0 / miso1 ?port p i/o pin 0 pp0 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 0 output. it can be configured as master input (during master mode) or slave output (during slave mode) pin miso of the serial peripheral interface 1 (spi1). 2.3.49 ps7 / ss0 ?port s i/o pin 7 ps7 is a general purpose input or output pin. it can be configured as the slave select pin ss of the serial peripheral interface 0 (spi0). 2.3.50 ps6 / sck0 ?port s i/o pin 6 ps6 is a general purpose input or output pin. it can be configured as the serial clock pin sck of the serial peripheral interface 0 (spi0).
device user guide ?9s12dt128dgv2/d v02.15 72 freescale semiconductor 2.3.51 ps5 / mosi0 ?port s i/o pin 5 ps5 is a general purpose input or output pin. it can be configured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 0 (spi0). 2.3.52 ps4 / miso0 ?port s i/o pin 4 ps4 is a general purpose input or output pin. it can be configured as master input (during master mode) or slave output pin (during slave mode) mosi of the serial peripheral interface 0 (spi0). 2.3.53 ps3 / txd1 ?port s i/o pin 3 ps3 is a general purpose input or output pin. it can be configured as the transmit pin txd of serial communication interface 1 (sci1). 2.3.54 ps2 / rxd1 ?port s i/o pin 2 ps2 is a general purpose input or output pin. it can be configured as the receive pin rxd of serial communication interface 1 (sci1). 2.3.55 ps1 / txd0 ?port s i/o pin 1 ps1 is a general purpose input or output pin. it can be configured as the transmit pin txd of serial communication interface 0 (sci0). 2.3.56 ps0 / rxd0 ?port s i/o pin 0 ps0 is a general purpose input or output pin. it can be configured as the receive pin rxd of serial communication interface 0 (sci0). 2.3.57 pt[7:0] / ioc[7:0] ?port t i/o pins [7:0] pt7-pt0 are general purpose input or output pins. they can be configured as input capture or output compare pins ioc7-ioc0 of the enhanced capture timer (ect). 2.4 power supply pins mc9s12dt128 power and ground pins are described below. table 2-2 mc9s12dt128 power and ground connection summary mnemonic pin number nominal voltage description 112-pin qfp vdd1, 2 13, 65 2.5v internal power and ground generated by internal regulator vss1, 2 14, 66 0v
device user guide ?9s12dt128dgv2/d v02.15 73 freescale semiconductor note: all vss pins must be connected together in the application. 2.4.1 vddx,vssx ?power & ground pins for i/o drivers external power and ground for i/o drivers. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily the mcu pins are loaded. 2.4.2 vddr, vssr ?power & ground pins for i/o drivers & for internal voltage regulator external power and ground for i/o drivers and input to the internal voltage regulator. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily the mcu pins are loaded. 2.4.3 vdd1, vdd2, vss1, vss2 ?internal logic power supply pins power is supplied to the mcu through vdd and vss. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. this 2.5v supply is derived from the internal voltage regulator. there is no static load on those pins allowed. the internal voltage regulator is turned off, if vregen is tied to ground. note: no load allowed except for bypass capacitors. vddr 41 5.0v external power and ground, supply to pin drivers and internal voltage regulator. vssr 40 0v vddx 107 5.0v external power and ground, supply to pin drivers. vssx 106 0v vdda 83 5.0v operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the a/d to be bypassed independently. vssa 86 0v vrl 85 0v reference voltages for the analog-to-digital converter. vrh 84 5.0v vddpll 43 2.5v provides operating voltage and ground for the phased-locked loop. this allows the supply voltage to the pll to be bypassed independently. internal power and ground generated by internal regulator. vsspll 45 0v vregen 97 5v internal voltage regulator enable/disable mnemonic pin number nominal voltage description 112-pin qfp
device user guide ?9s12dt128dgv2/d v02.15 74 freescale semiconductor 2.4.4 vdda, vssa ?power supply pins for atd and vreg vdda, vssa are the power supply and ground input pins for the voltage regulator and the analog to digital converter. it also provides the reference for the internal voltage regulator. this allows the supply voltage to the atd and the reference voltage to be bypassed independently. 2.4.5 vrh, vrl ?atd reference voltage input pins vrh and vrl are the reference voltage input pins for the analog to digital converter. 2.4.6 vddpll, vsspll ?power supply pins for pll provides operating voltage and ground for the oscillator and the phased-locked loop. this allows the supply voltage to the oscillator and pll to be bypassed independently.this 2.5v voltage is generated by the internal voltage regulator. note: no load allowed except for bypass capacitors. 2.4.7 vregen ?on chip voltage regulator enable enables the internal 5v to 2.5v voltage regulator. if this pin is tied low, vdd1,2 and vddpll must be supplied externally.
device user guide ?9s12dt128dgv2/d v02.15 75 freescale semiconductor section 3 system clock description 3.1 overview the clock and reset generator provides the internal clock signals for the core and all peripheral modules. figure 3-1 shows the clock connections from the crg to all modules. consult the crg block user guide for details on clock generation. figure 3-1 clock connections crg bus clock core clock extal xtal oscillator clock hcs12 core iic ram sci0, sci1 pwm atd0, 1 bf flash ect bdlc spi0, 1 can0, 1, 4 pim eeprom bdm mebi int cpu bkp mmc
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device user guide ?9s12dt128dgv2/d v02.15 77 freescale semiconductor section 4 modes of operation 4.1 overview eight possible modes determine the operating configuration of the mc9s12dt128. each mode has an associated default memory map and external bus configuration controlled by a further pin. three low power modes exist for the device. 4.2 chip configuration summary the operating mode out of reset is determined by the states of the modc, modb, and moda pins during reset ( (table 4-1) ). the modc, modb, and moda bits in the mode register show the current operating mode and provide limited mode switching during operation. the states of the modc, modb, and moda pins are latched into these bits on the rising edge of the reset signal. the romctl signal allows the setting of the romon bit in the misc register thus controlling whether the internal flash is visible in the memory map. romon = 1 mean the flash is visible in the memory map. the state of the romctl pin is latched into the romon bit in the misc register on the rising edge of the reset signal. for further explanation on the modes refer to the hcs12 multiplexed external bus interface block guide. table 4-1 mode selection bkgd = modc pe6 = modb pe5 = moda pk7 = romctl romon bit mode description 0 0 0 x 1 special single chip, bdm allowed and active. bdm is allowed in all other modes but a serial command is required to make bdm active. 0 0 1 0 1 emulation expanded narrow, bdm allowed 1 0 0 1 0 x 0 special test (expanded wide), bdm allowed 0 1 1 0 1 emulation expanded wide, bdm allowed 1 0 1 0 0 x 1 normal single chip, bdm allowed 1 0 1 0 0 normal expanded narrow, bdm allowed 1 1 1 1 0 x 1 special peripheral; bdm allowed but bus operations would cause bus con?cts (must not be used) 1 1 1 0 0 normal expanded wide, bdm allowed 1 1 table 4-2 clock selection based on pe7 pe7 = xclks description 1 colpitts oscillator selected 0 pierce oscillator/external clock selected
device user guide ?9s12dt128dgv2/d v02.15 78 freescale semiconductor 4.3 security the device will make available a security feature preventing the unauthorized read and write of the memory contents. this feature allows: protection of the contents of flash, protection of the contents of eeprom, operation in single-chip mode, no bdm possible operation from external memory with internal flash and eeprom disabled. the user must be reminded that part of the security must lie with the user? code. an extreme example would be user? code that dumps the contents of the internal program. this code would defeat the purpose of security. at the same time the user may also wish to put a back door in the user? program. an example of this is the user downloads a key through the sci which allows access to a programming routine that updates parameters stored in eeprom. 4.3.1 securing the microcontroller once the user has programmed the flash and eeprom (if desired), the part can be secured by programming the security bits located in the flash module. these non-volatile bits will keep the part secured through resetting the part and through powering down the part. the security byte resides in a portion of the flash array. check the flash block user guide for more details on the security configuration. 4.3.2 operation of the secured microcontroller 4.3.2.1 normal single chip mode this will be the most common usage of the secured part. everything will appear the same as if the part was not secured with the exception of bdm operation. the bdm operation will be blocked. 4.3.2.2 executing from external memory the user may wish to execute from external space with a secured microcontroller. this is accomplished by resetting directly into expanded mode. the internal flash and eeprom will be disabled. bdm operations will be blocked. table 4-3 voltage regulator vregen vregen description 1 internal voltage regulator enabled 0 internal voltage regulator disabled, vdd1,2 and vddpll must be supplied externally with 2.5v
device user guide ?9s12dt128dgv2/d v02.15 79 freescale semiconductor 4.3.3 unsecuring the microcontroller in order to unsecure the microcontroller, the internal flash and eeprom must be erased. this can be done through an external program in expanded mode or via a .sequence of bdm commands. unsecuring is also possible via the backdoor key access. refer to flash block guide for details. once the user has erased the flash and eeprom, the part can be reset into special single chip mode. this invokes a program that verifies the erasure of the internal flash and eeprom. once this program completes, the user can erase and program the flash security bits to the unsecured state. this is generally done through the bdm, but the user could also change to expanded mode (by writing the mode bits through the bdm) and jumping to an external program (again through bdm commands). note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again. 4.4 low power modes the microcontroller features three main low power modes. consult the respective block user guide for information on the module behavior in stop, pseudo stop, and wait mode. an important source of information about the clock system is the clock and reset generator user guide (crg). 4.4.1 stop executing the cpu stop instruction stops all clocks and the oscillator thus putting the chip in fully static mode. wake up from this mode can be done via reset or external interrupts. 4.4.2 pseudo stop this mode is entered by executing the cpu stop instruction. in this mode the oscillator is still running and the real time interrupt (rti) or watchdog (cop) sub module can stay active. other peripherals are turned off. this mode consumes more current than the full stop mode, but the wake up time from this mode is significantly shorter. 4.4.3 wait this mode is entered by executing the cpu wai instruction. in this mode the cpu will not execute instructions. the internal cpu signals (address and databus) will be fully static. all peripherals stay active. for further power consumption the peripherals can individually turn off their local clocks. 4.4.4 run although this is not a low power mode, unused peripheral modules should not be enabled in order to save power.
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device user guide ?9s12dt128dgv2/d v02.15 81 freescale semiconductor section 5 resets and interrupts 5.1 overview consult the exception processing section of the cpu reference manual for information on resets and interrupts. 5.2 vectors 5.2.1 vector table (table 5-1) lists interrupt sources and vectors in default order of priority. table 5-1 interrupt vector locations vector address interrupt source ccr mask local enable hprio value to elevate $fffe, $ffff reset none none $fffc, $fffd clock monitor fail reset none copctl (cme, fcme) $fffa, $fffb cop failure reset none cop rate select $fff8, $fff9 unimplemented instruction trap none none $fff6, $fff7 swi none none $fff4, $fff5 xirq / bf high priority sync pulse x-bit none / bfrier (xsynie) $fff2, $fff3 irq i-bit intcr (irqen) $f2 $fff0, $fff1 real time interrupt i-bit crgint (rtie) $f0 $ffee, $ffef enhanced capture timer channel 0 i-bit tie (c0i) $ee $ffec, $ffed enhanced capture timer channel 1 i-bit tie (c1i) $ec $ffea, $ffeb enhanced capture timer channel 2 i-bit tie (c2i) $ea $ffe8, $ffe9 enhanced capture timer channel 3 i-bit tie (c3i) $e8 $ffe6, $ffe7 enhanced capture timer channel 4 i-bit tie (c4i) $e6 $ffe4, $ffe5 enhanced capture timer channel 5 i-bit tie (c5i) $e4 $ffe2, $ffe3 enhanced capture timer channel 6 i-bit tie (c6i) $e2 $ffe0, $ffe1 enhanced capture timer channel 7 i-bit tie (c7i) $e0 $ffde, $ffdf enhanced capture timer over?w i-bit tscr2 (tof) $de $ffdc, $ffdd pulse accumulator a over?w i-bit pactl (paovi) $dc $ffda, $ffdb pulse accumulator input edge i-bit pactl (pai) $da $ffd8, $ffd9 spi0 i-bit spicr1 (spie, sptie) $d8 $ffd6, $ffd7 sci0 i-bit scicr2 (tie, tcie, rie, ilie) $d6 $ffd4, $ffd5 sci1 i-bit scicr2 (tie, tcie, rie, ilie) $d4 $ffd2, $ffd3 atd0 i-bit atdctl2 (ascie) $d2 $ffd0, $ffd1 atd1 i-bit atdctl2 (ascie) $d0 $ffce, $ffcf port j i-bit piej (piej7, piej6, piej1, piej0) $ce $ffcc, $ffcd port h i-bit pieh (pieh7-0) $cc
device user guide ?9s12dt128dgv2/d v02.15 82 freescale semiconductor 5.3 effects of reset when a reset occurs, mcu registers and control bits are changed to known start-up states. refer to the respective module block user guides for register reset states. 5.3.1 i/o pins refer to the hcs12 multiplexed external bus interface (mebi) block guide for mode dependent pin configuration of port a, b, e and k out of reset. refer to the pim block user guide for reset configurations of all peripheral module ports. $ffca, $ffcb modulus down counter under?w i-bit mcctl (mczi) $ca $ffc8, $ffc9 pulse accumulator b over?w i-bit pbctl (pbovi) $c8 $ffc6, $ffc7 crg pll lock i-bit pllcr (lockie) $c6 $ffc4, $ffc5 crg self clock mode i-bit pllcr (scmie) $c4 $ffc2, $ffc3 bdlc i-bit dlcbcr1 (ie) $c2 $ffc0, $ffc1 iic bus i-bit ibcr (ibie) $c0 $ffbe, $ffbf spi1 i-bit spicr1 (spie, sptie) $be $ffbc, $ffbd reserved $ffba, $ffbb eeprom i-bit ecnfg (ccie, cbeie) $ba $ffb8, $ffb9 flash i-bit fcnfg (ccie, cbeie) $b8 $ffb6, $ffb7 can0 wake-up i-bit canrier (wupie) $b6 $ffb4, $ffb5 can0 errors i-bit canrier (cscie, ovrie) $b4 $ffb2, $ffb3 can0 receive i-bit canrier (rxfie) $b2 $ffb0, $ffb1 can0 transmit i-bit cantier (txeie[2:0]) $b0 $ffae, $ffaf can1 wake-up i-bit canrier (wupie) $ae $ffac, $ffad can1 errors i-bit canrier (cscie, ovrie) $ac $ffaa, $ffab can1 receive i-bit canrier (rxfie) $aa $ffa8, $ffa9 can1 transmit i-bit cantier (txeie[2:0]) $a8 $ffa6, $ffa7 bf receive fifo not empty i-bit bfrier (rcvfie) $a6 $ffa4, $ffa5 bf receive i-bit bfbufctl[15:0] (iena) $a4 $ffa2, $ffa3 bf synchronization i-bit bfrier (synaie, synnie) $a2 $ffa0, $ffa1 bf general i-bit bfbufctl[15:0] (iena), bfgier (ovrnie, errie, syneie, synlie, illpie, lockie, wakeie) bfrier (slmmie) $a0 $ff98, $ff9f reserved $ff96, $ff97 can4 wake-up i-bit canrier (wupie) $96 $ff94, $ff95 can4 errors i-bit canrier (cscie, ovrie) $94 $ff92, $ff93 can4 receive i-bit canrier (rxfie) $92 $ff90, $ff91 can4 transmit i-bit cantier (txeie[2:0]) $90 $ff8e, $ff8f port p interrupt i-bit piep (piep7-0) $8e $ff8c, $ff8d pwm emergency shutdown i-bit pwmsdn (pwmie) $8c $ff80 to $ff8b reserved
device user guide ?9s12dt128dgv2/d v02.15 83 freescale semiconductor note: for devices assembled in 80-pin qfp packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. refer to table 2-1 for affected pins. 5.3.2 memory refer to table 1-1 for locations of the memories depending on the operating mode after reset. the ram array is not automatically initialized out of reset.
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device user guide ?9s12dt128dgv2/d v02.15 85 freescale semiconductor section 6 hcs12 core block description 6.1 cpu block description consult the cpu reference manual for information on the cpu. 6.1.1 device-specific information when the cpu reference manual refers to cycles this is equivalent to bus clock periods. so 1 cycle is equivalent to 1 bus clock period. 6.2 hcs12 module mapping control (mmc) block description consult the mmc block guide for information on the hcs12 module mapping control module. 6.2.1 device-specific information initee reset state: $01 bits ee11-ee15 are "write once in normal and emulation modes and write anytime in special modes". ppage reset state: $00 register is "write anytime in all modes". memsiz0 reset state: $13 memsiz1 reset state: $80 6.3 hcs12 multiplexed external bus interface (mebi) block description consult the mebi block guide for information on hcs12 multiplexed external bus interface module. 6.3.1 device-specific information pucr reset state: $90
device user guide ?9s12dt128dgv2/d v02.15 86 freescale semiconductor 6.4 hcs12 interrupt (int) block description consult the int block guide for information on the hcs12 interrupt module. 6.5 hcs12 background debug module (bdm) block description consult the bdm block guide for information on the hcs12 background debug module. 6.5.1 device-specific information when the bdm block guide refers to alternate clock this is equivalent to oscillator clock . 6.6 hcs12 breakpoint (bkp) block description consult the bkp block guide for information on the hcs12 breakpoint module. section 7 clock and reset generator (crg) block description consult the crg block user guide for information about the clock and reset generator module. 7.1 device-specific information the low voltage reset feature of the crg is not available on this device. section 8 oscillator (osc) block description consult the osc block user guide for information about the oscillator module. 8.1 device-specific information the xclks input signal is active low (see 2.3.12 pe / noacc / xclks ? port e i/o pin 7 ). section 9 enhanced capture timer (ect) block description
device user guide ?9s12dt128dgv2/d v02.15 87 freescale semiconductor consult the ect_16b8c block user guide for information about the enhanced capture timer module.when the ect_16b8c block user guide refers to freeze mode this is equivalent to active bdm mode . section 10 analog to digital converter (atd) block description there are two analog to digital converters (atd1 and atd0) implemented on the mc9s12dt128. consult the atd_10b8c block user guide for information about each analog to digital converter module. when the atd_10b8c block user guide refers to freeze mode this is equivalent to active bdm mode . section 11 inter-ic bus (iic) block description consult the iic block user guide for information about the inter-ic bus module. section 12 serial communications interface (sci) block description there are two serial communications interfaces (sci1 and sci0) implemented on the mc9s12dt128 device. consult the sci block user guide for information about each serial communications interface module. section 13 serial peripheral interface (spi) block description there are two serial peripheral interfaces (spi1 and spi0) implemented on mc9s12dt128. consult the spi block user guide for information about each serial peripheral interface module. section 14 j1850 (bdlc) block description consult the bdlc block user guide for information about the j1850 module. section 15 byteflight (bf) block description consult the bf block user guide for information about the 10 mbps byteflight module.
device user guide ?9s12dt128dgv2/d v02.15 88 freescale semiconductor 15.1 device-specific information the read-only module version register (bfmvr) contains the current version number of $80. section 16 pulse width modulator (pwm) block description consult the pwm_8b8c block user guide for information about the pulse width modulator module. when the pwm_8b8c block user guide refers to freeze mode this is equivalent to active bdm mode . section 17 flash eeprom 128k block description consult the fts128k block user guide for information about the flash module. the "s12 lrae" is a generic load ram and execute (lrae) program which will be programmed into the flash memory of this device during manufacture. this lrae program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using can or sci after it is assembled on the pcb. use of the lrae program is at the discretion of the end user and, if not required, it must simply be erased prior to flash programming. for more details of the s12 lrae and its implementation, please see the s12 lrea application note (an2546/d). it is planned that most hc9s12 devices manufactured after q1 of 2004 will be shipped with the s12 lrae programmed in the flash . exact details of the changeover (ie blank to programmed) for each product will be communicated in advance via gpcn and will be traceable by the customer via datecode marking on the device. please contact freescale sales if you have any additional questions. section 18 eeprom 2k block description consult the eets2k block user guide for information about the eeprom module. section 19 ram block description this module supports single-cycle misaligned word accesses without wait states. section 20 mscan block description there are three mscan modules (can4, can1 and can0) implemented on the mc9s12dt128. consult the mscan block user guide for information about the motorola scalable can module.
device user guide ?9s12dt128dgv2/d v02.15 89 freescale semiconductor section 21 port integration module (pim) block description consult the pim_9dtb128 block user guide for information about the port integration module. section 22 voltage regulator (vreg) block description consult the vreg block user guide for information about the dual output linear voltage regulator. section 23 printed circuit board layout proposal the pcb must be carefully laid out to ensure proper operation of the voltage regulator as well as of the mcu itself. the following rules must be observed: every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (c1 c6). central point of the ground star should be the vssr pin. table 23-1 suggested external component values component purpose type value c1 vdd1 ?ter cap ceramic x7r 100 ?220nf c2 vdd2 ?ter cap ceramic x7r 100 ?220nf c3 vdda ?ter cap ceramic x7r 100nf c4 vddr ?ter cap x7r/tantalum >= 100nf c5 vddpll ?ter cap ceramic x7r 100nf c6 vddx ?ter cap x7r/tantalum >= 100nf c7 osc load cap c8 osc load cap c9 / c s pll loop ?ter cap see pll speci?ation chapter c10 / c p pll loop ?ter cap c11 / c dc dc cutoff cap colpitts mode only, if recommended by quartz manufacturer r1 / r pll loop ?ter res see pll speci?ation chapter r2 / r b pierce mode only r3 / r s q1 quartz
device user guide ?9s12dt128dgv2/d v02.15 90 freescale semiconductor use low ohmic low inductance connections between vss1, vss2 and vssr. vsspll must be directly connected to vssr. keep traces of vsspll, extal and xtal as short as possible and occupied board area for c7, c8, c11 and q1 as small as possible. do not place other signals or supplies underneath area occupied by c7, c8, c10 and q1 and the connection area to the mcu. central power input should be fed in at the vdda/vssa pins.
device user guide ?9s12dt128dgv2/d v02.15 91 freescale semiconductor figure 23-1 recommended pcb layout for 112lqfp colpitts oscillator c5 c4 c1 c6 c3 c2 c8 c7 q1 c10 c9 r1 vddx vssx vddr vssr vdd1 vss1 vdd2 vss2 vddpll vsspll vdda vssa vregen c11
device user guide ?9s12dt128dgv2/d v02.15 92 freescale semiconductor figure 23-2 recommended pcb layout for 80qfp (mc9s12dg128e, mc9s12dg128, mc9s12dj128e, mc9s12dj128, mc9s12a128, sc515847, sc515848, sc101161dg, sc101161dj, sc102203, and sc102204) colpitts oscillator c5 c4 c3 c2 c8 c7 c10 c9 r1 c11 c6 c1 q1 vdd1 vss1 vss2 vdd2 vssr vddr vsspll vddpll vdda vssa vssx vregen vddx
device user guide ?9s12dt128dgv2/d v02.15 93 freescale semiconductor figure 23-3 recommended pcb layout for 112lqfp pierce oscillator c5 c4 c1 c6 c3 c2 c10 c9 r1 vddx vssx vddr vssr vdd1 vss1 vdd2 vss2 vddpll vsspll vdda vssa vregen r2 c7 r3 c8 q1
device user guide ?9s12dt128dgv2/d v02.15 94 freescale semiconductor figure 23-4 recommended pcb layout for 80qfp (mc9s12dg128e, mc9s12dg128, mc9s12dj128e, mc9s12dj128, mc9s12a128, sc515847, sc515848, sc101161dg, sc101161dj, sc102203, and sc102204) pierce oscillator c5 c4 c3 c2 c10 c9 r1 c6 c1 vdd1 vss1 vss2 vdd2 vssr vddr vsspll vddpll vdda vssa vssx vregen vddx r2 c7 r3 c8 q1 vsspll
device user guide ?9s12dt128dgv2/d v02.15 95 freescale semiconductor figure 23-5 recommended pcb layout for 80qfp (mc9s12db128, sc515846, and sc102202) pierce oscillator c5 c4 c3 c2 c10 c9 r1 c6 c1 vdd1 vss1 vss2 vdd2 vssr vddr vsspll vddpll vdda vssa vssx vregen vddx r2 c7 r3 c8 q1 vsspll
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device user guide ?9s12dt128dgv2/d v02.15 97 freescale semiconductor appendix a electrical characteristics a.1 general this introduction is intended to give an overview on several common topics like power supply, current injection etc. a.1.1 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. p: those parameters are guaranteed during production testing on each individual device. c: those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. they are regularly verified by production monitors. t: those parameters are achieved by design characterization on a small sample size from typical devices. all values shown in the typical column are within this category. d: those parameters are derived mainly from simulations. a.1.2 power supply the mc9s12dt128 utilizes several pins to supply power to the i/o ports, a/d converter, oscillator, pll and internal logic. the vdda, vssa pair supplies the a/d converter and the resistor ladder of the internal voltage regulator. the vddx, vssx, vddr and vssr pairs supply the i/o pins, vddr supplies also the internal voltage regulator. vdd1, vss1, vdd2 and vss2 are the supply pins for the digital logic, vddpll, vsspll supply the oscillator and the pll. vss1 and vss2 are internally connected by metal. vdda, vddx, vddr as well as vssa, vssx, vssr are connected by anti-parallel diodes for esd protection.
device user guide ?9s12dt128dgv2/d v02.15 98 freescale semiconductor note: in the following context vdd5 is used for either vdda, vddr and vddx; vss5 is used for either vssa, vssr and vssx unless otherwise noted. idd5 denotes the sum of the currents flowing into the vdda, vddx and vddr pins. vdd is used for vdd1, vdd2 and vddpll, vss is used for vss1, vss2 and vsspll. idd is used for the sum of the currents flowing into vdd1 and vdd2. a.1.3 pins there are four groups of functional pins. a.1.3.1 5v i/o pins those i/o pins have a nominal level of 5v. this class of pins is comprised of all port i/o pins, the analog inputs, bkgd pin and the reset inputs.the internal structure of all those pins is identical, however some of the functionality may be disabled. e.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. a.1.3.2 analog reference this class is made up by the two vrh and vrl pins. a.1.3.3 oscillator the pins xfc, extal, xtal dedicated to the oscillator have a nominal 2.5v level. they are supplied by vddpll. a.1.3.4 test this pin is used for production testing only. a.1.3.5 vregen this pin is used to enable the on chip voltage regulator. a.1.4 current injection power supply must maintain regulation within operating v dd5 or v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd5 ) is greater than i dd5 , the injection current may flow out of vdd5 and could result in external power supply going out of regulation. insure external vdd5 load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.
device user guide ?9s12dt128dgv2/d v02.15 99 freescale semiconductor a.1.5 absolute maximum ratings absolute maximum ratings are stress ratings only. a functional operation under or outside those maxima is not guaranteed. stress beyond those limits may affect the reliability or cause permanent damage of the device. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss5 or v dd5 ). a.1.6 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model. table a-1 absolute maximum ratings 1 notes : 1. beyond absolute maximum ratings device might be damaged. num rating symbol min max unit 1 i/o, regulator and analog supply voltage v dd5 -0.3 6.0 v 2 digital logic supply voltage 2 2. the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. v dd -0.3 3.0 v 3 pll supply voltage (2) v ddpll -0.3 3.0 v 4 voltage difference vddx to vddr and vdda ? vddx -0.3 0.3 v 5 voltage difference vssx to vssr and vssa ? vssx -0.3 0.3 v 6 digital i/o input voltage v in -0.3 6.0 v 7 analog reference v rh, v rl -0.3 6.0 v 8 xfc, extal, xtal inputs v ilv -0.3 3.0 v 9 test input v test -0.3 10.0 v 10 instantaneous maximum current single pin limit for all digital i/o pins 3 3. all digital i/o pins are internally clamped to v ssx and v ddx , v ssr and v ddr or v ssa and v dda . i d -25 +25 ma 11 instantaneous maximum current single pin limit for xfc, extal, xtal 4 4. those pins are internally clamped to v sspll and v ddpll . i dl -25 +25 ma 12 instantaneous maximum current single pin limit for test 5 5. this pin is clamped low to v ssx , but not clamped high. this pin must be tied low in applications. i dt -0.25 0 ma 13 storage temperature range t stg ?65 155 c
device user guide ?9s12dt128dgv2/d v02.15 100 freescale semiconductor a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. a.1.7 operating conditions this chapter describes the operating conditions of the device. unless otherwise noted those conditions apply to all the following data. note: please refer to the temperature rating of the device (c, v, m) with regards to the ambient temperature t a and the junction temperature t j . for power dissipation table a-2 esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ohm storage capacitance c 100 pf number of pulse per pin positive negative 3 3 machine series resistance r1 0 ohm storage capacitance c 200 pf number of pulse per pin positive negative 3 3 latch-up minimum input voltage limit ?.5 v maximum input voltage limit 7.5 v table a-3 esd and latch-up protection characteristics num c rating symbol min max unit 1 c human body model (hbm) v hbm 2000 v 2 c machine model (mm) v mm 200 v 3 c charge device model (cdm) v cdm 500 v 4 c latch-up current at 125 c positive negative i lat +100 ?00 ma 5 c latch-up current at 27 c positive negative i lat +200 ?00 ma
device user guide ?9s12dt128dgv2/d v02.15 101 freescale semiconductor calculations refer to section a.1.8 power dissipation and thermal characteristics . a.1.8 power dissipation and thermal characteristics power dissipation and thermal characteristics are closely related. the user must assure that the maximum operating junction temperature is not exceeded. the average chip-junction temperature (t j ) in c can be obtained from: table a-4 operating conditions rating symbol min typ max unit i/o, regulator and analog supply voltage v dd5 4.5 5 5.25 v digital logic supply voltage 1 notes : 1. the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the given operating range applies when this regulator is disabled and the device is powered from an external source. v dd 2.35 2.5 2.75 v pll supply voltage 1 v ddpll 2.25 2.5 2.75 v voltage difference vddx to vddr and vdda ? vddx -0.1 0 0.1 v voltage difference vssx to vssr and vssa ? vssx -0.1 0 0.1 v bus frequency f bus 0.25 2 2. some blocks e.g. atd (conversion) and nvms (program/erase) require higher bus frequencies for proper oper - ation. - 25 mhz mc9s12dt128 c operating junction temperature range t j -40 - 100 c operating ambient temperature range 3 3. please refer to section a.1.8 power dissipation and thermal characteristics for more details about the rela - tion between ambient temperature t a and device junction temperature t j . t a -40 27 85 c mc9s12dt128 v operating junction temperature range t j -40 - 120 c operating ambient temperature range 3 t a -40 27 105 c mc9s12dt128 m operating junction temperature range t j -40 - 140 c operating ambient temperature range 3 t a -40 27 125 c t j t a p d ja ? () + = t j junction temperature, [ c ] = t a ambient temperature, [ c ] =
device user guide ?9s12dt128dgv2/d v02.15 102 freescale semiconductor the total power dissipation can be calculated from: two cases with internal voltage regulator enabled and disabled must be considered: 1. internal voltage regulator disabled which is the sum of all output currents on i/o ports associated with vddx and vddr. for r dson is valid: respectively 2. internal voltage regulator enabled i ddr is the current shown in (table a-7) and not the overall current flowing into vddr, which additionally contains the current flowing into the external loads with output high. which is the sum of all output currents on i/o ports associated with vddx and vddr. p d total chip power dissipation, [w] = ja package thermal resistance, [ c/w] = p d p int p io + = p int chip internal power dissipation, [w] = p int i dd v dd ? i ddpll v ddpll ? i dda +v dda ? + = p io r dson i i io i 2 ? = r dson v ol i ol ------------ for outputs driven low ; = r dson v dd5 v oh i oh ------------------------------------ for outputs driven high ; = p int i ddr v ddr ? i dda v dda ? + = p io r dson i i io i 2 ? =
device user guide ?9s12dt128dgv2/d v02.15 103 freescale semiconductor a.1.9 i/o characteristics this section describes the characteristics of all 5v i/o pins. all parameters are not always applicable, e.g. not all pins feature pull up/down resistances. table a-5 thermal package characteristics 1 notes : 1. the values for thermal resistance are achieved by package simulations num c rating symbol min typ max unit 1 t thermal resistance lqfp112, single sided pcb 2 2. pc board according to eia/jedec standard 51-3 ja 54 o c/w 2 t thermal resistance lqfp112, double sided pcb with 2 internal planes 3 3. pc board according to eia/jedec standard 51-7 ja 41 o c/w 3 t junction to board lqfp112 jb 31 o c/w 4 t junction to case lqfp112 jc 11 o c/w 5 t junction to package top lqfp112 jt 2 o c/w 6 t thermal resistance qfp 80, single sided pcb ja 51 o c/w 7 t thermal resistance qfp 80, double sided pcb with 2 internal planes ja 41 o c/w 8 t junction to board qfp80 jb 27 o c/w 9 t junction to case qfp80 jc 14 o c/w 10 t junction to package top qfp80 jt 3 o c/w
device user guide ?9s12dt128dgv2/d v02.15 104 freescale semiconductor a.1.10 supply currents this section describes the current consumption characteristics of the device as well as the conditions for the measurements. table a-6 5v i/o characteristics conditions are shown in (table a-4) unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 v t input high voltage v ih v dd5 + 0.3 2 p input low voltage v il 0.35*v dd5 v t input low voltage v il v ss5 0.3 v 3 c input hysteresis v hys 250 mv 4 p input leakage current (pins in high ohmic input mode) v in = v dd5 or v ss5 i in -1.0 1.0 a 5 c p output high voltage (pins in output mode) partial drive i oh = ?.0ma full drive i oh = ?0.0ma v oh v dd5 ?0.8 v 6 c p output low voltage (pins in output mode) partial drive i ol = +2.0ma full drive i ol = +10.0ma v ol 0.8 v 7 p internal pull up device current, tested at v il max. i pul ?30 a 8 c internal pull up device current, tested at v ih min. i puh ?0 a 9 p internal pull down device current, tested at v ih min. i pdh 130 a 10 c internal pull down device current, tested at v il max. i pdl 10 a 11 d input capacitance c in 6 pf 12 t injection current 1 single pin limit total device limit. sum of all injected currents notes : 1. refer to section a.1.4 current injection , for more details i ics i icp ?.5 ?5 2.5 25 ma 13 p port h, j, p interrupt input pulse ?tered 2 2. parameter only applies in stop or pseudo stop mode. t pulse 3 s 14 p port h, j, p interrupt input pulse passed 2 t pulse 10 s
device user guide ?9s12dt128dgv2/d v02.15 105 freescale semiconductor a.1.10.1 measurement conditions all measurements are without output loads. unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25mhz bus frequency using a 4mhz oscillator in colpitts mode. production testing is performed using a square wave signal at the extal input. a.1.10.2 additional remarks in expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. no generally applicable numbers can be given. a very good estimate is to take the single chip currents and add the currents due to the external loads. table a-7 supply current characteristics conditions are shown in (table a-4) unless otherwise noted num c rating symbol min typ max unit 1 p run supply currents single chip, internal regulator enabled i dd5 55 ma 2 p p wait supply current all modules enabled, pll on only rti enabled (1) i ddw 30 5 ma 3 c p c c p c p c p pseudo stop current (rti and cop disabled) 1 , 2 -40 c 27 c 70 c 85 c ??temp option 100 c 105 c ??temp option 120 c 125 c ??temp option 140 c i ddps 370 400 450 550 600 650 800 850 1200 500 1600 2100 5000 a 4 c c c c c c c pseudo stop current (rti and cop enabled) (1) , (2) -40 c 27 c 70 c 85 c 105 c 125 c 140 c i ddps 570 600 650 750 850 1200 1500 a 5 c p c c p c p c p stop current (2) -40 c 27 c 70 c 85 c ??temp option 100 c 105 c ??temp option 120 c 125 c ??temp option 140 c i dds 12 25 100 130 160 200 350 400 600 100 1200 1700 5000 a
device user guide ?9s12dt128dgv2/d v02.15 106 freescale semiconductor notes : 1. pll off, oscillator in colpitts mode 2. at those low power dissipation levels t j = t a can be assumed
device user guide ?9s12dt128dgv2/d v02.15 107 freescale semiconductor a.2 atd characteristics this section describes the characteristics of the analog to digital converter. a.2.1 atd operating characteristics the (table a-8) shows conditions under which the atd operates. the following constraints exist to obtain full-scale, full range results: v ssa v rl v in v rh v dda . this constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. if the input level goes outside of this range it will effectively be clipped. table a-8 atd operating characteristics a.2.2 factors influencing accuracy three factors ?source resistance, source capacitance and current injection ?have an influence on the accuracy of the atd. a.2.2.1 source resistance: due to the input pin leakage current as specified in (table a-6) in conjunction with the source resistance there will be a voltage drop from the signal source to the atd input. the maximum source resistance r s conditions are shown in (table a-4) unless otherwise noted num c rating symbol min typ max unit 1 d reference potential low high v rl v rh v ssa v dda /2 v dda /2 v dda v v 2 c differential reference voltage 1 notes : 1. full accuracy is not guaranteed when differential voltage is less than 4.50v v rh -v rl 4.50 5.00 5.25 v 3 d atd clock frequency f atdclk 0.5 2.0 mhz 4 d atd 10-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f atdclk 2. the minimum time assumes a final sample period of 2 atd clocks cycles while the maximum time assumes a final sample period of 16 atd clocks. n conv10 t conv10 14 7 28 14 cycles s 5 d atd 8-bit conversion period clock cycles (2) conv, time at 2.0mhz atd clock f atdclk n conv8 t conv8 12 6 26 13 cycles s 6 d stop recovery time (v dda =5.0 volts) t sr 20 s 7 p reference supply current (both atd modules on) i ref 0.75 ma 8 p reference supply current (only one atd module on) i ref 0.375 ma
device user guide ?9s12dt128dgv2/d v02.15 108 freescale semiconductor specifies results in an error of less than 1/2 lsb (2.5mv) at the maximum leakage current. if device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. a.2.2.2 source capacitance when sampling an additional internal capacitor is switched to the input. this can cause a voltage drop due to charge sharing with the external and the pin capacitance. for a maximum sampling error of the input voltage 1lsb, then the external filter capacitor, c f 1024 * (c ins ?c inn ). a.2.2.3 current injection there are two cases to consider. 1. a current is injected into the channel being converted. the channel being stressed has conversion values of $3ff ($ff in 8-bit mode) for analog inputs greater than v rh and $000 for values less than v rl unless the current is higher than specified as disruptive conditions. 2. current is injected into pins in the neighborhood of the channel being converted. a portion of this current is picked up by the channel (coupling ratio k), this additional current impacts the accuracy of the conversion depending on the source resistance. the additional input voltage error on the converted channel can be calculated as v err = k * r s * i inj , with i inj being the sum of the currents injected into the two pins adjacent to the converted channel. table a-9 atd electrical characteristics conditions are shown in (table a-4) unless otherwise noted num c rating symbol min typ max unit 1 c max input source resistance r s - - 1 k ? 2 t total input capacitance non sampling sampling c inn c ins 10 22 pf 3 c disruptive analog input current i na -2.5 2.5 ma 4 c coupling ratio positive current injection k p 10 -4 a/a 5 c coupling ratio negative current injection k n 10 -2 a/a
device user guide ?9s12dt128dgv2/d v02.15 109 freescale semiconductor a.2.3 atd accuracy (table a-10) specifies the atd conversion performance excluding any errors due to current injection, input capacitance and source resistance. table a-10 atd conversion performance for the following definitions see also figure a-1 . differential non-linearity (dnl) is defined as the difference between two adjacent switching steps. the integral non-linearity (inl) is defined as the sum of all dnls: conditions are shown in (table a-4) unless otherwise noted v ref = v rh - v rl = 5.12v. resulting to one 8 bit count = 20mv and one 10 bit count = 5mv f atdclk = 2.0mhz num c rating symbol min typ max unit 1 p 10-bit resolution lsb 5 mv 2 p 10-bit differential nonlinearity dnl ? 1 counts 3 p 10-bit integral nonlinearity inl ?.5 1.5 2.5 counts 4 p 10-bit absolute error 1 notes : 1. these values include the quantization error which is inherently 1/2 count for any a/d converter. ae -3 2.0 3 counts 5 p 8-bit resolution lsb 20 mv 6 p 8-bit differential nonlinearity dnl ?.5 0.5 counts 7 p 8-bit integral nonlinearity inl ?.0 0.5 1.0 counts 8 p 8-bit absolute error (1) ae -1.5 1.0 1.5 counts dnl i () v i v i1 1lsb ------------------------ 1 = inl n () dnl i () i1 = n v n v 0 1lsb ------------------- - n ==
device user guide ?9s12dt128dgv2/d v02.15 110 freescale semiconductor figure a-1 atd accuracy definitions note: figure a-1 shows only definitions, for specification values refer to table a-10 . 1 5 vin mv 10 15 20 25 30 35 40 5085 5090 5095 5100 5105 5110 5115 5120 5065 5070 5075 5080 5060 0 3 2 5 4 7 6 45 $3f7 $3f9 $3f8 $3fb $3fa $3fd $3fc $3fe $3ff $3f4 $3f6 $3f5 8 9 1 2 $ff $fe $fd $3f3 10-bit resolution 8-bit resolution ideal transfer curve 10-bit transfer curve 8-bit transfer curve 5055 10-bit absolute error boundary 8-bit absolute error boundary lsb v i-1 v i dnl
device user guide ?9s12dt128dgv2/d v02.15 111 freescale semiconductor a.3 nvm, flash and eeprom note: unless otherwise noted the abbreviation nvm (non volatile memory) is used for both flash and eeprom. a.3.1 nvm timing the time base for all nvm program or erase operations is derived from the oscillator. a minimum oscillator frequency f nvmosc is required for performing program or erase operations. the nvm modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. attempting to program or erase the nvm modules at a lower frequency a full program or erase transition is not assured. the flash and eeprom program and erase operations are timed using a clock derived from the oscillator using the fclkdiv and eclkdiv registers respectively. the frequency of this clock must be set within the limits specified as f nvmop . the minimum program and erase times shown in (table a-11) are calculated for maximum f nvmop and maximum f bus . the maximum times are calculated for minimum f nvmop and a f bus of 2mhz. a.3.1.1 single word programming the programming time for single word programming is dependant on the bus frequency as a well as on the frequency f nvmop and can be calculated according to the following formula. a.3.1.2 row programming this applies only to the flash where up to 32 words in a row can be programmed consecutively by keeping the command pipeline filled. the time to program a consecutive word can be calculated as: the time to program a whole row is: row programming is more than 2 times faster than single word programming. a.3.1.3 sector erase erasing a 512 byte flash sector or a 4 byte eeprom sector takes: t swpgm 9 1 f nvmop --------------------- ? 25 1 f bus ---------- ? + = t bwpgm 4 1 f nvmop --------------------- ? 9 1 f bus ---------- ? + = t brpgm t swpgm 31 t bwpgm ? + =
device user guide ?9s12dt128dgv2/d v02.15 112 freescale semiconductor the setup time can be ignored for this operation. a.3.1.4 mass erase erasing a nvm block takes: the setup time can be ignored for this operation. a.3.1.5 blank check the time it takes to perform a blank check on the flash or eeprom is dependant on the location of the first non-blank word starting at relative address zero. it takes one bus cycle per word to verify plus a setup of the command. table a-11 nvm timing characteristics conditions are shown in (table a-4) unless otherwise noted num c rating symbol min typ max unit 1 d external oscillator clock f nvmosc 0.5 50 1 notes : 1. restrictions for oscillator in crystal mode apply! mhz 2 d bus frequency for programming or erase operations f nvmbus 1 mhz 3 d operating frequency f nvmop 150 200 khz 4 p single word programming time t swpgm 46 2 2. minimum programming times are achieved under maximum nvm operating frequency f nvmop and maximum bus frequency f bus . 74.5 3 3. maximum erase and programming times are achieved under particular combinations of f nvmop and bus frequency f bus . refer to formulae in sections section a.3.1.1 single word programming - section a.3.1.4 mass erase for guidance. s 5 d flash row programming consecutive word 4 4. row programming operations are not applicable to eeprom t bwpgm 20.4 (2) 31 (3) s 6 d flash row programming time for 32 words (4) t brpgm 678.4 (2) 1035.5 (3) s 7 p sector erase time t era 20 5 5. minimum erase times are achieved under maximum nvm operating frequency f nvmop . 26.7 (3) ms 8 p mass erase time t mass 100 (5) 133 (3) ms 9 d blank check time flash per block t check 11 6 6. minimum time, if first word in the array is not blank 32778 7 7. maximum time to complete check on an erased block t cyc 10 d blank check time eeprom per block t check 11 (6) 1034 (7) t cyc t era 4000 1 f nvmop --------------------- ? t mass 20000 1 f nvmop --------------------- ? t check location t cyc 10 t cyc ? + ?
device user guide ?9s12dt128dgv2/d v02.15 113 freescale semiconductor a.3.2 nvm reliability the reliability of the nvm blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. the failure rates for data retention and program/erase cycling are specified at the operating conditions noted. the program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed.
device user guide ?9s12dt128dgv2/d v02.15 114 freescale semiconductor table a-12 nvm reliability characteristics 1 notes : 1. t javg will not exeed 85 c considering a typical temperature profile over the lifetime of a consumer, industrial or automotive application. conditions are shown in (table a-4) unless otherwise noted num c rating symbol min typ max unit flash reliability characteristics 1 c data retention after 10,000 program/erase cycles at an average junction temperature of t javg 85 c t flret 15 100 2 2. typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how freescale defines typical data retention, please refer to engineering bulletin eb618. years 2 c data retention with <100 program/erase cycles at an average junction temperature t javg 85 c 20 100 2 3 c number of program/erase cycles (?0 c t j 0 c) n fl 10,000 cycles 4 c number of program/erase cycles (0 c t j 140 c) 10,000 100,000 3 3. spec table quotes typical endurance evaluated at 25 c for this product family, typical endurance at various temperature can be estimated using the graph below. for additional information on how freescale defines typical endurance, please refer to engineering bulletin eb619. eeprom reliability characteristics 5 c data retention after up to 100,000 program/erase cycles at an average junction temperature of t javg 85 c t eepret 15 100 2 years 6 c data retention with <100 program/erase cycles at an average junction temperature t javg 85 c 20 100 2 7 c number of program/erase cycles (?0 c t j 0 c) n eep 10,000 cycles 8 c number of program/erase cycles (0 c < t j 140 c) 100,000 300,000 3
device user guide ?9s12dt128dgv2/d v02.15 115 freescale semiconductor figure a-2 typical endurance vs temperature typical endurance [10 3 cycles] operating temperature t j [ c] 0 50 100 150 200 250 300 350 400 450 500 -40 -20 0 20 40 60 80 100 120 140 ------ flash ------ eeprom
device user guide ?9s12dt128dgv2/d v02.15 116 freescale semiconductor
device user guide ?9s12dt128dgv2/d v02.15 117 freescale semiconductor a.4 voltage regulator the on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. no external dc load is allowed. table a-13 voltage regulator recommended load capacitances rating symbol min typ max unit load capacitance on vdd1, 2 c lvdd 220 nf load capacitance on vddpll c lvddfcpll 220 nf
device user guide ?9s12dt128dgv2/d v02.15 118 freescale semiconductor
device user guide ?9s12dt128dgv2/d v02.15 119 freescale semiconductor a.5 reset, oscillator and pll this section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked-loop (pll). a.5.1 startup (table a-14) summarizes several startup characteristics explained in this section. detailed description of the startup behavior can be found in the clock and reset generator (crg) block user guide. table a-14 startup characteristics a.5.1.1 por the release level v porr and the assert level v pora are derived from the v dd supply. they are also valid if the device is powered externally. after releasing the por reset the oscillator and the clock quality check are started. if after a time t cqout no valid oscillation is detected, the mcu will start using the internal self clock. the fastest startup time possible is given by n uposc . a.5.1.2 sram data retention provided an appropriate external reset signal is applied to the mcu, preventing the cpu from executing code when vdd5 is out of specification limits, the sram contents integrity is guaranteed if after the reset the porf bit in the crg flags register has not been set. a.5.1.3 external reset when external reset is asserted for a time greater than pw rstl the crg module generates an internal reset, and the cpu starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. a.5.1.4 stop recovery out of stop the controller can be woken up by an external interrupt. a clock quality check as after por is performed before releasing the clocks to the system. conditions are shown in (table a-4) unless otherwise noted num c rating symbol min typ max unit 1 t por release level v porr 2.07 v 2 t por assert level v pora 0.97 v 3 d reset input pulse width, minimum input time pw rstl 2 t osc 4 d startup from reset n rst 192 196 n osc 5 d interrupt pulse width, irq edge-sensitive mode pw irq 20 ns 6 d wait recovery startup time t wrs 14 t cyc
device user guide ?9s12dt128dgv2/d v02.15 120 freescale semiconductor a.5.1.5 pseudo stop and wait recovery the recovery from pseudo stop and wait are essentially the same since the oscillator was not stopped in both modes. the controller can be woken up by internal or external interrupts. after t wrs the cpu starts fetching the interrupt vector. a.5.2 oscillator the device features an internal colpitts and pierce oscillator. the selection of colpitts oscillator or pierce oscillator/external clock depends on the xclks signal which is sampled during reset.by asserting the xclks input during reset this oscillator can be bypassed allowing the input of a square wave. before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, stop or oscillator fail. t cqout specifies the maximum time before switching to the internal self clock mode after por or stop if a proper oscillation is not detected. the quality check also determines the minimum oscillator start-up time t uposc . the device also features a clock monitor. a
device user guide ?9s12dt128dgv2/d v02.15 121 freescale semiconductor clock monitor failure is asserted if the frequency of the incoming clock signal is below the assert frequency f cmfa. a.5.3 phase locked loop the oscillator provides the reference clock for the pll. the plls voltage controlled oscillator (vco) is also the system clock source in self clock mode. a.5.3.1 xfc component selection this section describes the selection of the xfc components to achieve a good filter characteristics. table a-15 oscillator characteristics conditions are shown in (table a-4) unless otherwise noted num c rating symbol min typ max unit 1a c crystal oscillator range (colpitts) f osc 0.5 16 mhz 1b c crystal oscillator range (pierce) 1 notes : 1. depending on the crystal a damping series resistor might be necessary f osc 0.5 40 mhz 2 p startup current i osc 100 a 3 c oscillator start-up time (colpitts) t uposc 8 2 2. f osc = 4mhz, c = 22pf. 100 3 3. maximum value is for extreme cases using high q, low frequency crystals ms 4 d clock quality check time-out t cqout 0.45 2.5 s 5 p clock monitor failure assert frequency f cmfa 50 100 200 khz 6 p external square wave input frequency 4 4. xclks =0 during reset f ext 0.5 50 mhz 7 d external square wave pulse width low t extl 9.5 ns 8 d external square wave pulse width high t exth 9.5 ns 9 d external square wave rise time t extr 1 ns 10 d external square wave fall time t extf 1 ns 11 d input capacitance (extal, xtal pins) c in 7 pf 12 c dc operating bias in colpitts con?uration on extal pin v dcbias 1.1 v 13 p extal pin input high voltage 4 v ih,extal 0.75*v ddpll v t extal pin input high voltage 4 v ih,extal v ddpll + 0.3 v 14 p extal pin input low voltage 4 v il,extal 0.25*v ddpll v t extal pin input low voltage 4 v il,extal v sspll - 0.3 v 15 c extal pin input hysteresis 4 v hys,extal 250 mv
device user guide ?9s12dt128dgv2/d v02.15 122 freescale semiconductor figure a-3 basic pll functional diagram the following procedure can be used to calculate the resistance and capacitance values using typical values for k 1 , f 1 and i ch from (table a-16) . the grey boxes show the calculation for f vco = 50mhz and f ref = 1mhz. e.g., these frequencies are used for f osc = 4mhz and a 25mhz bus clock. the vco gain at the desired vco frequency is approximated by: the phase detector relationship is given by: i ch is the current in tracking mode. the loop bandwidth f c should be chosen to fulfill the gardner? stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response. f osc 1 refdv+1 f ref phase detector vco k v 1 synr+1 f vco loop divider k 1 2 ? f cmp c s r c p vddpll xfc pin k v k 1 e f 1 f vco () k 1 1v ? ----------------------- ? = 100 e 60 50 () 100 ----------------------- - ? = = -90.48mhz/v k i ch k v ? = = 316.7hz/ ? f c 2 f ref ?? 1 2 + + ?? ?? ? ------------------------------------------ 1 10 ------ f c f ref 410 ? -------------- 0.9 = () ; < < f c < 25khz
device user guide ?9s12dt128dgv2/d v02.15 123 freescale semiconductor and finally the frequency relationship is defined as with the above values the resistance can be calculated. the example is shown for a loop bandwidth f c =10khz: the capacitance c s can now be calculated as: the capacitance c p should be chosen in the range of: a.5.3.2 jitter information the basic functionality of the pll is shown in figure a-3 . with each transition of the clock f cmp , the deviation from the reference clock f ref is measured and input voltage to the vco is adjusted accordingly.the adjustment is done continuously with no abrupt changes in the clock output frequency. noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. this jitter affects the real minimum and maximum clock periods as illustrated in figure a-4 . n f vco f ref ------------- 2 s y n r 1 + () ? == = 50 r 2 nf c ??? k ---------------------------- - = = 2* *50*10khz/(316.7hz/ ? ) =9.9k ? =~ 10k ? c s 2 2 ? f c r ?? --------------------- - 0.516 f c r ? -------------- - 0.9 = () ; = = 5.19nf =~ 4.7nf c s 20 ? c p c s 10 ? ? c p = 470pf
device user guide ?9s12dt128dgv2/d v02.15 124 freescale semiconductor figure a-4 jitter definitions the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n). defining the jitter as: for n < 100, the following equation is a good fit for the maximum jitter: figure a-5 maximum bus clock jitter approximation 2 3 n-1 n 1 0 t nom t max1 t min1 t maxn t minn jn () max 1 t max n () nt nom ? --------------------- 1 t min n () nt nom ? -------------------- - , ?? ?? ?? = j n () j 1 n -------- j 2 + = 1 5 10 20 n j (n)
device user guide ?9s12dt128dgv2/d v02.15 125 freescale semiconductor this is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. table a-16 pll characteristics conditions are shown in (table a-4) unless otherwise noted num c rating symbol min typ max unit 1 p self clock mode frequency f scm 1 5.5 mhz 2 d vco locking range f vco 8 50 mhz 3 d lock detector transition from acquisition to tracking mode |? trk | 3 4 % 1 notes : 1. % deviation from target frequency 4 d lock detection |? lock | 0 1.5 % (1) 5 d un-lock detection |? unl | 0.5 2.5 % (1) 6 d lock detector transition from tracking to acquisition mode |? unt | 6 8 % (1) 7 c pllon total stabilization delay (auto mode) 2 2. f osc = 4mhz, f bus = 25mhz equivalent f vco = 50mhz: refdv = #$03, synr = #$018, cs = 4.7nf, cp = 470pf, rs = 10k ? . t stab 0.5 ms 8 d pllon acquisition mode stabilization delay (2) t acq 0.3 ms 9 d pllon tracking mode stabilization delay (2) t al 0.2 ms 10 d fitting parameter vco loop gain k 1 -100 mhz/v 11 d fitting parameter vco loop frequency f 1 60 mhz 12 d charge pump current acquisition mode | i ch | 38.5 a 13 d charge pump current tracking mode | i ch | 3.5 a 14 c jitter ? parameter 1 (2) j 1 1.1 % 15 c jitter ? parameter 2 (2) j 2 0.13 %
device user guide ?9s12dt128dgv2/d v02.15 126 freescale semiconductor
device user guide ?9s12dt128dgv2/d v02.15 127 freescale semiconductor a.6 mscan table a-17 mscan wake-up pulse characteristics conditions are shown in (table a-4) unless otherwise noted num c rating symbol min typ max unit 1 p mscan wake-up dominant pulse ?tered t wup 2 s 2 p mscan wake-up dominant pulse pass t wup 5 s
device user guide ?9s12dt128dgv2/d v02.15 128 freescale semiconductor
device user guide ?9s12dt128dgv2/d v02.15 129 freescale semiconductor a.7 spi a.7.1 master mode figure a-6 and figure a-7 illustrate the master mode timing. timing values are shown in (table a-18) . figure a-6 spi master timing (cpha = 0) sck (output) sck (output) miso (input) mosi (output) ss 1 (output) 1 9 5 6 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 10 4 4 2 9 (cpol = 0) (cpol = 1) 3 11 12 1.if configured as an output. 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb.
device user guide ?9s12dt128dgv2/d v02.15 130 freescale semiconductor figure a-7 spi master timing (cpha =1) table a-18 spi master mode timing characteristics 1 notes : 1. the numbers 7, 8 in the column labeled ?um?are missing. this has been done on purpose to be consistent between the master and the slave timing shown in (table a-19) . conditions are shown in (table a-4) unless otherwise noted, c load = 200pf on all outputs num c rating symbol min typ max unit 1 p operating frequency f op dc 1 / 2 f bus 1 p sck period t sck = 1./f op t sck 4 2048 t bus 2 d enable lead time t lead 1 / 2 t sck 3 d enable lag time t lag 1 / 2 t sck 4 d clock (sck) high or low time t wsck t bus ? 30 1024 t bus ns 5 d data setup time (inputs) t su 25 ns 6 d data hold time (inputs) t hi 0 ns 9 d data valid (after sck edge) t v 25 ns 10 d data hold time (outputs) t ho 0 ns 11 d rise time inputs and outputs t r 25 ns 12 d fall time inputs and outputs t f 25 ns sck (output) sck (output) miso (input) mosi (output) 1 5 6 msb in 2 bit 6 . . . 1 lsb in master msb out 2 master lsb out bit 6 . . . 1 4 4 9 11 12 10 port data (cpol = 0) (cpol = 1) port data ss 1 (output) 2 12 11 3 1.if configured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb.
device user guide ?9s12dt128dgv2/d v02.15 131 freescale semiconductor a.7.2 slave mode figure a-8 and figure a-9 illustrate the slave mode timing. timing values are shown in (table a-19) . figure a-8 spi slave timing (cpha = 0) figure a-9 spi slave timing (cpha =1) sck (input) sck (input) mosi (input) miso (output) ss (input) 1 9 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 10 4 4 2 7 (cpol = 0) (cpol = 1) 3 12 slave 12 11 10 11 8 sck (input) sck (input) mosi (input) miso (output) 1 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 9 11 12 10 (cpol = 0) (cpol = 1) ss (input) 2 12 11 3 slave 7 8
device user guide ?9s12dt128dgv2/d v02.15 132 freescale semiconductor table a-19 spi slave mode timing characteristics conditions are shown in (table a-4) unless otherwise noted, cload = 200pf on all outputs num c rating symbol min typ max unit 1 p operating frequency f op dc 1 / 4 f bus 1 p sck period t sck = 1./f op t sck 4 2048 t bus 2 d enable lead time t lead 1 t cyc 3 d enable lag time t lag 1 t cyc 4 d clock (sck) high or low time t wsck t cyc ? 30 ns 5 d data setup time (inputs) t su 25 ns 6 d data hold time (inputs) t hi 25 ns 7 d slave access time t a 1 t cyc 8 d slave miso disable time t dis 1 t cyc 9 d data valid (after sck edge) t v 25 ns 10 d data hold time (outputs) t ho 0 ns 11 d rise time inputs and outputs t r 25 ns 12 d fall time inputs and outputs t f 25 ns
device user guide ?9s12dt128dgv2/d v02.15 133 freescale semiconductor a.8 external bus timing a timing diagram of the external multiplexed-bus is illustrated in figure a-10 with the actual timing values shown on table (table a-20) . all major bus signals are included in the diagram. while both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle. a.8.1 general multiplexed bus timing the expanded bus timings are highly dependent on the load conditions. the timing parameters shown assume a balanced load across all outputs.
device user guide ?9s12dt128dgv2/d v02.15 134 freescale semiconductor figure a-10 general external bus timing addr/data (read) addr/data (write) addr data data 5 10 11 8 16 6 eclk 1, 2 3 4 addr data data 12 15 9 7 14 13 ecs 21 20 22 23 non-multiplexed 17 19 lstrb 29 no a cc 32 pipo0 pipo1, pe6,5 35 18 27 28 30 33 36 31 34 r/ w 24 26 25 addresses pe4 pa, pb pa, pb pk5:0 pk7 pe2 pe3 pe7
device user guide ?9s12dt128dgv2/d v02.15 135 freescale semiconductor table a-20 expanded bus timing characteristics conditions are shown in (table a-4) unless otherwise noted, c load = 50pf num c rating symbol min typ max unit 1 p frequency of operation (e-clock) f o 0 25.0 mhz 2 p cycle time t cyc 40 ns 3 d pulse width, e low pw el 19 ns 4 d pulse width, e high 1 pw eh 19 ns 5 d address delay time t ad 8 ns 6 d address valid time to e rise (pw el ? ad ) t av 11 ns 7 d muxed address hold time t mah 2 ns 8 d address hold to data valid t ahds 7 ns 9 d data hold to address t dha 2 ns 10 d read data setup time t dsr 13 ns 11 d read data hold time t dhr 0 ns 12 d write data delay time t ddw 7 ns 13 d write data hold time t dhw 2 ns 14 d write data setup time (1) (pw eh ? ddw ) t dsw 12 ns 15 d address access time (1) (t cyc ? ad ? dsr ) t acca 19 ns 16 d e high access time (1) (pw eh ? dsr ) t acce 6 ns 17 d non-multiplexed address delay time t nad 6 ns 18 d non-muxed address valid to e rise (pw el ? nad ) t nav 15 ns 19 d non-multiplexed address hold time t nah 2 ns 20 d chip select delay time t csd 16 ns 21 d chip select access time (1) (t cyc ? csd ? dsr ) t accs 11 ns 22 d chip select hold time t csh 2 ns 23 d chip select negated time t csn 8 ns 24 d read/write delay time t rwd 7 ns 25 d read/write valid time to e rise (pw el ? rwd ) t rwv 14 ns 26 d read/write hold time t rwh 2 ns 27 d low strobe delay time t lsd 7 ns 28 d low strobe valid time to e rise (pw el ? lsd ) t lsv 14 ns 29 d low strobe hold time t lsh 2 ns 30 d noacc strobe delay time t nod 7 ns 31 d noacc valid time to e rise (pw el ? nod ) t nov 14 ns
device user guide ?9s12dt128dgv2/d v02.15 136 freescale semiconductor 32 d noacc hold time t noh 2 ns 33 d ipipo[1:0] delay time t p0d 2 7 ns 34 d ipipo[1:0] valid time to e rise (pw el ? p0d ) t p0v 11 ns 35 d ipipo[1:0] delay time (1) (pw eh -t p1v ) t p1d 2 25 ns 36 d ipipo[1:0] valid time to e fall t p1v 11 ns notes : 1. affected by clock stretch: add n x t cyc where n=0,1,2 or 3, depending on the number of clock stretches. table a-20 expanded bus timing characteristics conditions are shown in (table a-4) unless otherwise noted, c load = 50pf num c rating symbol min typ max unit
device user guide ?9s12dt128dgv2/d v02.15 137 freescale semiconductor appendix b package information b.1 general this section provides the physical dimensions of the mc9s12dt128 packages.
device user guide ?9s12dt128dgv2/d v02.15 138 freescale semiconductor b.2 112-pin lqfp package figure 23-6 112-pin lqfp mechanical dimensions (case no. 987) dim a min max 20.000 bsc millimeters a1 10.000 bsc b 20.000 bsc b1 10.000 bsc c --- 1.600 c1 0.050 0.150 c2 1.350 1.450 d 0.270 0.370 e 0.450 0.750 f 0.270 0.330 g 0.650 bsc j 0.090 0.170 k 0.500 ref p 0.325 bsc r1 0.100 0.200 r2 0.100 0.200 s 22.000 bsc s1 11.000 bsc v 22.000 bsc v1 11.000 bsc y 0.250 ref z 1.000 ref aa 0.090 0.160 11 11 13 7 13 view y l-m 0.20 n t 4x 4x 28 tips pin 1 ident 1 112 85 84 28 57 29 56 b v v1 b1 a1 s1 a s view ab 0.10 3 c c2 2 0.050 seating plane gage plane 1 view ab c1 (z) (y) e (k) r2 r1 0.25 j1 view y j1 p g 108x 4x section j1-j1 base rotated 90 counterclockwise metal j aa f d l-m m 0.13 n t 1 2 3 c l l-m 0.20 n t l n m t t 112x x x=l, m or n r r notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b include mold mismatch. 6. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.46. 8 3 0
device user guide ?9s12dt128dgv2/d v02.15 139 freescale semiconductor b.3 80-pin qfp package figure 1 80-pin qfp mechanical dimensions (case no. 841b) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -a-, -b- and -d- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -c-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. section b-b 61 60 detail a l 41 40 80 -a- l -d- a s a-b m 0.20 d s h 0.05 a-b s 120 21 -b- b v j f n d view rotated 90 detail a b b p -a-,-b-,-d- e h g m m detail c seating plane -c- c datum plane 0.10 -h- datum plane -h- u t r q k w x detail c dim min max millimeters a 13.90 14.10 b 13.90 14.10 c 2.15 2.45 d 0.22 0.38 e 2.00 2.40 f 0.22 0.33 g 0.65 bsc h --- 0.25 j 0.13 0.23 k 0.65 0.95 l 12.35 ref m 5 10 n 0.13 0.17 p 0.325 bsc q 0 7 r 0.13 0.30 s 16.95 17.45 t 0.13 --- u 0 --- v 16.95 17.45 w 0.35 0.45 x 1.6 ref s a-b m 0.20 d s c s a-b m 0.20 d s h 0.05 d s a-b m 0.20 d s c s a-b m 0.20 d s c
device user guide ?9s12dt128dgv2/d v02.15 140 freescale semiconductor
device user guide ?9s12dt128dgv2/d v02.15 141 freescale semiconductor user guide end sheet
9s12dt128dgv2/d v02.15, 05 jul 2005 how to reach us: usa/europe/locations not listed: freescale semiconductor literature distribution p.o. box 5405, denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: freescale semiconductor japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/paci?: freescale semiconductor h.k. ltd. 2 dai king street tai po industrial estate tai po, n.t. hong kong 852-26668334 learn more: for more information about freescale semiconductor products, please visit http://www.freescale.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical?parameters which may be provided in freescale semiconductor data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals?must be validated for each customer application by customers technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ?freescale semiconductor, inc. 2004. final page of 142 pages

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